Commit c9629203 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-oct-2018-part-2-v2' into staging 



MIPS queue for October 2018 - part 2 - v2

# gpg: Signature made Wed 24 Oct 2018 14:22:54 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-oct-2018-part-2-v2: (33 commits)
  target/mips: Fix decoding of ALIGN and DALIGN instructions
  target/mips: Fix the title of translate.c
  linux-user/mips: Recognize the R5900 CPU model
  target/mips: Define the R5900 CPU
  tests/tcg/mips: Add tests for R5900 DIVU1
  tests/tcg/mips: Add tests for R5900 DIV1
  tests/tcg/mips: Add tests for R5900 MTLO1 and MTHI1
  tests/tcg/mips: Add tests for R5900 MFLO1 and MFHI1
  tests/tcg/mips: Add tests for R5900 three-operand MULTU1
  tests/tcg/mips: Add tests for R5900 three-operand MULT1
  tests/tcg/mips: Add tests for R5900 three-operand MULTU
  tests/tcg/mips: Add tests for R5900 three-operand MULT
  target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only
  target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV
  target/mips: Support R5900 DIV1 and DIVU1 instructions
  target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions
  target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions
  target/mips: Support R5900 three-operand MULT and MULTU instructions
  target/mips: Add a placeholder for R5900 MMI3 instruction subclass
  target/mips: Add a placeholder for R5900 MMI2 instruction subclass
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 18e19564 373ecd38

linux-user/mips/target_elf.h

+3 −0
Original line number Diff line number Diff line
@@ -12,6 +12,9 @@ static inline const char *cpu_get_model(uint32_t eflags) 
    if ((eflags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R6) {

        return "mips32r6-generic";

    }

    if ((eflags & EF_MIPS_MACH) == EF_MIPS_MACH_5900) {

        return "R5900";

    }

    return "24Kf";

}

#endif

target/mips/mips-defs.h

+3 −0
Original line number Diff line number Diff line
@@ -64,9 +64,11 @@ 
#define INSN_LOONGSON2E   0x0001000000000000ULL

#define INSN_LOONGSON2F   0x0002000000000000ULL

#define INSN_VR54XX       0x0004000000000000ULL

#define INSN_R5900        0x0008000000000000ULL

/*

 *   bits 56-63: vendor-specific ASEs

 */

#define ASE_MMI           0x0100000000000000ULL



/* MIPS CPU defines. */

#define		CPU_MIPS1	(ISA_MIPS1)
@@ -74,6 +76,7 @@ 
#define		CPU_MIPS3	(CPU_MIPS2 | ISA_MIPS3)

#define		CPU_MIPS4	(CPU_MIPS3 | ISA_MIPS4)

#define		CPU_VR54XX	(CPU_MIPS4 | INSN_VR54XX)

#define         CPU_R5900       (CPU_MIPS3 | INSN_R5900)

#define		CPU_LOONGSON2E  (CPU_MIPS3 | INSN_LOONGSON2E)

#define		CPU_LOONGSON2F  (CPU_MIPS3 | INSN_LOONGSON2F)

target/mips/translate.c

+846 −19

File changed.

Preview size limit exceeded, changes collapsed.

target/mips/translate_init.inc.c

+59 −0
Original line number Diff line number Diff line
@@ -410,6 +410,65 @@ const mips_def_t mips_defs[] = 
        .insn_flags = CPU_MIPS32R5 | ASE_MSA,

        .mmu_type = MMU_TYPE_R4000,

    },

    {

        /*

         * The Toshiba TX System RISC TX79 Core Architecture manual

         *

         * https://wiki.qemu.org/File:C790.pdf

         *

         * describes the C790 processor that is a follow-up to the R5900.

         * There are a few notable differences in that the R5900 FPU

         *

         * - is not IEEE 754-1985 compliant,

         * - does not implement double format, and

         * - its machine code is nonstandard.

         */

        .name = "R5900",

        .CP0_PRid = 0x00002E00,

        /* No L2 cache, icache size 32k, dcache size 32k, uncached coherency. */

        .CP0_Config0 = (0x3 << 9) | (0x3 << 6) | (0x2 << CP0C0_K0),

        .CP0_Status_rw_bitmask = 0xF4C79C1F,

#ifdef CONFIG_USER_ONLY

        /*

         * R5900 hardware traps to the Linux kernel for IEEE 754-1985 and LL/SC

         * emulation. For user only, QEMU is the kernel, so we emulate the traps

         * by simply emulating the instructions directly.

         *

         * Note: Config1 is only used internally, the R5900 has only Config0.

         */

        .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),

        .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,

        .CP0_LLAddr_shift = 4,

        .CP1_fcr0 = (0x38 << FCR0_PRID) | (0x0 << FCR0_REV),

        .CP1_fcr31 = 0,

        .CP1_fcr31_rw_bitmask = 0x0183FFFF,

#else

        /*

         * The R5900 COP1 FPU implements single-precision floating-point

         * operations but is not entirely IEEE 754-1985 compatible. In

         * particular,

         *

         * - NaN (not a number) and +/- infinities are not supported;

         * - exception mechanisms are not fully supported;

         * - denormalized numbers are not supported;

         * - rounding towards nearest and +/- infinities are not supported;

         * - computed results usually differs in the least significant bit;

         * - saturations can differ more than the least significant bit.

         *

         * Since only rounding towards zero is supported, the two least

         * significant bits of FCR31 are hardwired to 01.

         *

         * FPU emulation is disabled here until it is implemented.

         *

         * Note: Config1 is only used internally, the R5900 has only Config0.

         */

        .CP0_Config1 = (47 << CP0C1_MMU),

#endif /* !CONFIG_USER_ONLY */

        .SEGBITS = 32,

        .PABITS = 32,

        .insn_flags = CPU_R5900 | ASE_MMI,

        .mmu_type = MMU_TYPE_R4000,

    },

    {

        /* A generic CPU supporting MIPS32 Release 6 ISA.

           FIXME: Support IEEE 754-2008 FP.

tests/tcg/mips/mipsr5900/Makefile

0 → 100644
+30 −0
Original line number Diff line number Diff line 
-include ../../config-host.mak



CROSS=mipsr5900el-unknown-linux-gnu-



SIM=qemu-mipsel

SIM_FLAGS=-cpu R5900



CC      = $(CROSS)gcc

CFLAGS  = -Wall -mabi=32 -march=r5900 -static



TESTCASES = div1.tst

TESTCASES += divu1.tst

TESTCASES += mflohi1.tst

TESTCASES += mtlohi1.tst

TESTCASES += mult.tst

TESTCASES += multu.tst



all: $(TESTCASES)



%.tst: %.c

	$(CC) $(CFLAGS) $< -o $@



check: $(TESTCASES)

	@for case in $(TESTCASES); do \

        echo $(SIM) $(SIM_FLAGS) ./$$case;\

        $(SIM) $(SIM_FLAGS) ./$$case; \

	done



clean:

	$(RM) -rf $(TESTCASES)