Commit c8232b39 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging 



pc,virtio,pci: fixes and updates

Most notably, this includes the TCO support for ICH: the last feature for 2.4
as we are entering the hard freeze.

Bugfixes only from now on.

virtio pci also gained cfg access capability - arguably a bugfix
since virtio spec makes it mandatory, but it's a big patch.

Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>

# gpg: Signature made Wed Jul  8 10:40:07 2015 BST using RSA key ID D28D5469
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>"
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>"

* remotes/mst/tags/for_upstream:
  tco-test: fix up config accesses and re-enable
  virtio fix cfg endian-ness for BE targets
  virtio-pci: implement cfg capability
  virtio: define virtio_pci_cfg_cap in header.
  pcie: Set the "link active" in the link status register
  pci_regs.h: import from linux
  virtio_net: reuse constants from linux
  hw/i386/pc: don't carry FDC from pc_basic_device_init() to pc_cmos_init()
  hw/i386/pc: reflect any FDC @ ioport 0x3f0 in the CMOS
  hw/i386/pc: factor out pc_cmos_init_floppy()
  ich9: implement strap SPKR pin logic
  tests: add testcase for TCO watchdog emulation
  ich9: add TCO interface emulation
  acpi: split out ICH ACPI support
  Revert "dataplane: allow virtio-1 devices"
  dataplane: fix cross-endian issues

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 62a3864e c4fc82bf

default-configs/i386-softmmu.mak

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ CONFIG_PCKBD=y 
CONFIG_FDC=y

CONFIG_ACPI=y

CONFIG_ACPI_X86=y

CONFIG_ACPI_X86_ICH=y

CONFIG_ACPI_MEMORY_HOTPLUG=y

CONFIG_ACPI_CPU_HOTPLUG=y

CONFIG_APM=y

default-configs/x86_64-softmmu.mak

+1 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ CONFIG_PCKBD=y 
CONFIG_FDC=y

CONFIG_ACPI=y

CONFIG_ACPI_X86=y

CONFIG_ACPI_X86_ICH=y

CONFIG_ACPI_MEMORY_HOTPLUG=y

CONFIG_ACPI_CPU_HOTPLUG=y

CONFIG_APM=y

hw/acpi/Makefile.objs

+2 −1
Original line number Diff line number Diff line 
common-obj-$(CONFIG_ACPI_X86) += core.o piix4.o ich9.o pcihp.o

common-obj-$(CONFIG_ACPI_X86) += core.o piix4.o pcihp.o

common-obj-$(CONFIG_ACPI_X86_ICH) += ich9.o tco.o

common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o

common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o

common-obj-$(CONFIG_ACPI) += acpi_interface.o

hw/acpi/ich9.c

+56 −1
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
#include "qemu/timer.h"

#include "sysemu/sysemu.h"

#include "hw/acpi/acpi.h"

#include "hw/acpi/tco.h"

#include "sysemu/kvm.h"

#include "exec/address-spaces.h"
@@ -92,8 +93,16 @@ static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val, 
                            unsigned width)

{

    ICH9LPCPMRegs *pm = opaque;

    TCOIORegs *tr = &pm->tco_regs;

    uint64_t tco_en;



    switch (addr) {

    case 0:

        tco_en = pm->smi_en & ICH9_PMIO_SMI_EN_TCO_EN;

        /* once TCO_LOCK bit is set, TCO_EN bit cannot be overwritten */

        if (tr->tco.cnt1 & TCO_LOCK) {

            val = (val & ~ICH9_PMIO_SMI_EN_TCO_EN) | tco_en;

        }

        pm->smi_en &= ~pm->smi_en_wmask;

        pm->smi_en |= (val & pm->smi_en_wmask);

        break;
@@ -159,6 +168,25 @@ static const VMStateDescription vmstate_memhp_state = { 
    }

};



static bool vmstate_test_use_tco(void *opaque)

{

    ICH9LPCPMRegs *s = opaque;

    return s->enable_tco;

}



static const VMStateDescription vmstate_tco_io_state = {

    .name = "ich9_pm/tco",

    .version_id = 1,

    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .needed = vmstate_test_use_tco,

    .fields      = (VMStateField[]) {

        VMSTATE_STRUCT(tco_regs, ICH9LPCPMRegs, 1, vmstate_tco_io_sts,

                       TCOIORegs),

        VMSTATE_END_OF_LIST()

    }

};



const VMStateDescription vmstate_ich9_pm = {

    .name = "ich9_pm",

    .version_id = 1,
@@ -179,6 +207,10 @@ const VMStateDescription vmstate_ich9_pm = { 
    .subsections = (const VMStateDescription*[]) {

        &vmstate_memhp_state,

        NULL

    },

    .subsections = (const VMStateDescription*[]) {

        &vmstate_tco_io_state,

        NULL

    }

};
@@ -209,7 +241,8 @@ static void pm_powerdown_req(Notifier *n, void *opaque) 
    acpi_pm1_evt_power_down(&pm->acpi_regs);

}



void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, bool smm_enabled,

void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,

                  bool smm_enabled, bool enable_tco,

                  qemu_irq sci_irq)

{

    memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
@@ -232,6 +265,12 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, bool smm_enabled, 
    memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);



    pm->smm_enabled = smm_enabled;



    pm->enable_tco = enable_tco;

    if (pm->enable_tco) {

        acpi_pm_tco_init(&pm->tco_regs, &pm->io);

    }



    pm->irq = sci_irq;

    qemu_register_reset(pm_reset, pm);

    pm->powerdown_notifier.notify = pm_powerdown_req;
@@ -352,6 +391,18 @@ out: 
    error_propagate(errp, local_err);

}



static bool ich9_pm_get_enable_tco(Object *obj, Error **errp)

{

    ICH9LPCState *s = ICH9_LPC_DEVICE(obj);

    return s->pm.enable_tco;

}



static void ich9_pm_set_enable_tco(Object *obj, bool value, Error **errp)

{

    ICH9LPCState *s = ICH9_LPC_DEVICE(obj);

    s->pm.enable_tco = value;

}



void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp)

{

    static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
@@ -383,6 +434,10 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp) 
                        ich9_pm_get_s4_val,

                        ich9_pm_set_s4_val,

                        NULL, pm, NULL);

    object_property_add_bool(obj, ACPI_PM_PROP_TCO_ENABLED,

                             ich9_pm_get_enable_tco,

                             ich9_pm_set_enable_tco,

                             NULL);

}



void ich9_pm_device_plug_cb(ICH9LPCPMRegs *pm, DeviceState *dev, Error **errp)

hw/acpi/tco.c

0 → 100644
+264 −0
Original line number Diff line number Diff line 
/*

 * QEMU ICH9 TCO emulation

 *

 * Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>

 *

 * This work is licensed under the terms of the GNU GPL, version 2 or later.

 * See the COPYING file in the top-level directory.

 */

#include "qemu-common.h"

#include "sysemu/watchdog.h"

#include "hw/i386/ich9.h"



#include "hw/acpi/tco.h"



//#define DEBUG



#ifdef DEBUG

#define TCO_DEBUG(fmt, ...)                                     \

    do {                                                        \

        fprintf(stderr, "%s "fmt, __func__, ## __VA_ARGS__);    \

    } while (0)

#else

#define TCO_DEBUG(fmt, ...) do { } while (0)

#endif



enum {

    TCO_RLD_DEFAULT         = 0x0000,

    TCO_DAT_IN_DEFAULT      = 0x00,

    TCO_DAT_OUT_DEFAULT     = 0x00,

    TCO1_STS_DEFAULT        = 0x0000,

    TCO2_STS_DEFAULT        = 0x0000,

    TCO1_CNT_DEFAULT        = 0x0000,

    TCO2_CNT_DEFAULT        = 0x0008,

    TCO_MESSAGE1_DEFAULT    = 0x00,

    TCO_MESSAGE2_DEFAULT    = 0x00,

    TCO_WDCNT_DEFAULT       = 0x00,

    TCO_TMR_DEFAULT         = 0x0004,

    SW_IRQ_GEN_DEFAULT      = 0x03,

};



static inline void tco_timer_reload(TCOIORegs *tr)

{

    tr->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +

        ((int64_t)(tr->tco.tmr & TCO_TMR_MASK) * TCO_TICK_NSEC);

    timer_mod(tr->tco_timer, tr->expire_time);

}



static inline void tco_timer_stop(TCOIORegs *tr)

{

    tr->expire_time = -1;

}



static void tco_timer_expired(void *opaque)

{

    TCOIORegs *tr = opaque;

    ICH9LPCPMRegs *pm = container_of(tr, ICH9LPCPMRegs, tco_regs);

    ICH9LPCState *lpc = container_of(pm, ICH9LPCState, pm);

    uint32_t gcs = pci_get_long(lpc->chip_config + ICH9_CC_GCS);



    tr->tco.rld = 0;

    tr->tco.sts1 |= TCO_TIMEOUT;

    if (++tr->timeouts_no == 2) {

        tr->tco.sts2 |= TCO_SECOND_TO_STS;

        tr->tco.sts2 |= TCO_BOOT_STS;

        tr->timeouts_no = 0;



        if (!lpc->pin_strap.spkr_hi && !(gcs & ICH9_CC_GCS_NO_REBOOT)) {

            watchdog_perform_action();

            tco_timer_stop(tr);

            return;

        }

    }



    if (pm->smi_en & ICH9_PMIO_SMI_EN_TCO_EN) {

        ich9_generate_smi();

    } else {

        ich9_generate_nmi();

    }

    tr->tco.rld = tr->tco.tmr;

    tco_timer_reload(tr);

}



/* NOTE: values of 0 or 1 will be ignored by ICH */

static inline int can_start_tco_timer(TCOIORegs *tr)

{

    return !(tr->tco.cnt1 & TCO_TMR_HLT) && tr->tco.tmr > 1;

}



static uint32_t tco_ioport_readw(TCOIORegs *tr, uint32_t addr)

{

    uint16_t rld;



    switch (addr) {

    case TCO_RLD:

        if (tr->expire_time != -1) {

            int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);

            int64_t elapsed = (tr->expire_time - now) / TCO_TICK_NSEC;

            rld = (uint16_t)elapsed | (tr->tco.rld & ~TCO_RLD_MASK);

        } else {

            rld = tr->tco.rld;

        }

        return rld;

    case TCO_DAT_IN:

        return tr->tco.din;

    case TCO_DAT_OUT:

        return tr->tco.dout;

    case TCO1_STS:

        return tr->tco.sts1;

    case TCO2_STS:

        return tr->tco.sts2;

    case TCO1_CNT:

        return tr->tco.cnt1;

    case TCO2_CNT:

        return tr->tco.cnt2;

    case TCO_MESSAGE1:

        return tr->tco.msg1;

    case TCO_MESSAGE2:

        return tr->tco.msg2;

    case TCO_WDCNT:

        return tr->tco.wdcnt;

    case TCO_TMR:

        return tr->tco.tmr;

    case SW_IRQ_GEN:

        return tr->sw_irq_gen;

    }

    return 0;

}



static void tco_ioport_writew(TCOIORegs *tr, uint32_t addr, uint32_t val)

{

    switch (addr) {

    case TCO_RLD:

        tr->timeouts_no = 0;

        if (can_start_tco_timer(tr)) {

            tr->tco.rld = tr->tco.tmr;

            tco_timer_reload(tr);

        } else {

            tr->tco.rld = val;

        }

        break;

    case TCO_DAT_IN:

        tr->tco.din = val;

        tr->tco.sts1 |= SW_TCO_SMI;

        ich9_generate_smi();

        break;

    case TCO_DAT_OUT:

        tr->tco.dout = val;

        tr->tco.sts1 |= TCO_INT_STS;

        /* TODO: cause an interrupt, as selected by the TCO_INT_SEL bits */

        break;

    case TCO1_STS:

        tr->tco.sts1 = val & TCO1_STS_MASK;

        break;

    case TCO2_STS:

        tr->tco.sts2 = val & TCO2_STS_MASK;

        break;

    case TCO1_CNT:

        val &= TCO1_CNT_MASK;

        /*

         * once TCO_LOCK bit is set, it can not be cleared by software. a reset

         * is required to change this bit from 1 to 0 -- it defaults to 0.

         */

        tr->tco.cnt1 = val | (tr->tco.cnt1 & TCO_LOCK);

        if (can_start_tco_timer(tr)) {

            tr->tco.rld = tr->tco.tmr;

            tco_timer_reload(tr);

        } else {

            tco_timer_stop(tr);

        }

        break;

    case TCO2_CNT:

        tr->tco.cnt2 = val;

        break;

    case TCO_MESSAGE1:

        tr->tco.msg1 = val;

        break;

    case TCO_MESSAGE2:

        tr->tco.msg2 = val;

        break;

    case TCO_WDCNT:

        tr->tco.wdcnt = val;

        break;

    case TCO_TMR:

        tr->tco.tmr = val;

        break;

    case SW_IRQ_GEN:

        tr->sw_irq_gen = val;

        break;

    }

}



static uint64_t tco_io_readw(void *opaque, hwaddr addr, unsigned width)

{

    TCOIORegs *tr = opaque;

    return tco_ioport_readw(tr, addr);

}



static void tco_io_writew(void *opaque, hwaddr addr, uint64_t val,

                          unsigned width)

{

    TCOIORegs *tr = opaque;

    tco_ioport_writew(tr, addr, val);

}



static const MemoryRegionOps tco_io_ops = {

    .read = tco_io_readw,

    .write = tco_io_writew,

    .valid.min_access_size = 1,

    .valid.max_access_size = 4,

    .impl.min_access_size = 1,

    .impl.max_access_size = 2,

    .endianness = DEVICE_LITTLE_ENDIAN,

};



void acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent)

{

    *tr = (TCOIORegs) {

        .tco = {

            .rld      = TCO_RLD_DEFAULT,

            .din      = TCO_DAT_IN_DEFAULT,

            .dout     = TCO_DAT_OUT_DEFAULT,

            .sts1     = TCO1_STS_DEFAULT,

            .sts2     = TCO2_STS_DEFAULT,

            .cnt1     = TCO1_CNT_DEFAULT,

            .cnt2     = TCO2_CNT_DEFAULT,

            .msg1     = TCO_MESSAGE1_DEFAULT,

            .msg2     = TCO_MESSAGE2_DEFAULT,

            .wdcnt    = TCO_WDCNT_DEFAULT,

            .tmr      = TCO_TMR_DEFAULT,

        },

        .sw_irq_gen    = SW_IRQ_GEN_DEFAULT,

        .tco_timer     = timer_new_ns(QEMU_CLOCK_VIRTUAL, tco_timer_expired, tr),

        .expire_time   = -1,

        .timeouts_no   = 0,

    };

    memory_region_init_io(&tr->io, memory_region_owner(parent),

                          &tco_io_ops, tr, "sm-tco", ICH9_PMIO_TCO_LEN);

    memory_region_add_subregion(parent, ICH9_PMIO_TCO_RLD, &tr->io);

}



const VMStateDescription vmstate_tco_io_sts = {

    .name = "tco io device status",

    .version_id = 1,

    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField[]) {

        VMSTATE_UINT16(tco.rld, TCOIORegs),

        VMSTATE_UINT8(tco.din, TCOIORegs),

        VMSTATE_UINT8(tco.dout, TCOIORegs),

        VMSTATE_UINT16(tco.sts1, TCOIORegs),

        VMSTATE_UINT16(tco.sts2, TCOIORegs),

        VMSTATE_UINT16(tco.cnt1, TCOIORegs),

        VMSTATE_UINT16(tco.cnt2, TCOIORegs),

        VMSTATE_UINT8(tco.msg1, TCOIORegs),

        VMSTATE_UINT8(tco.msg2, TCOIORegs),

        VMSTATE_UINT8(tco.wdcnt, TCOIORegs),

        VMSTATE_UINT16(tco.tmr, TCOIORegs),

        VMSTATE_UINT8(sw_irq_gen, TCOIORegs),

        VMSTATE_TIMER_PTR(tco_timer, TCOIORegs),

        VMSTATE_INT64(expire_time, TCOIORegs),

        VMSTATE_UINT8(timeouts_no, TCOIORegs),

        VMSTATE_END_OF_LIST()

    }

};