Commit c658b94f authored by Andreas Färber's avatar Andreas Färber
Browse files

cpu: Turn cpu_unassigned_access() into a CPUState hook 



Use it for all targets, but be careful not to pass invalid CPUState.
cpu_single_env can be NULL, e.g. on Xen.

Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
parent ce927ed9

cputlb.c

+9 −6
Original line number Diff line number Diff line
@@ -331,12 +331,15 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) 
    pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;

    mr = iotlb_to_region(pd);

    if (memory_region_is_unassigned(mr)) {

#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC)

        cpu_unassigned_access(env1, addr, 0, 1, 0, 4);

#else

        CPUState *cpu = ENV_GET_CPU(env1);

        CPUClass *cc = CPU_GET_CLASS(cpu);



        if (cc->do_unassigned_access) {

            cc->do_unassigned_access(cpu, addr, false, true, 0, 4);

        } else {

            cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x"

                      TARGET_FMT_lx "\n", addr);

#endif

        }

    }

    p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);

    return qemu_ram_addr_from_host_nofail(p);

hw/alpha/typhoon.c

+10 −4
Original line number Diff line number Diff line
@@ -197,7 +197,8 @@ static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) 
        break;



    default:

        cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);

        cpu = CPU(alpha_env_get_cpu(cpu_single_env));

        cpu_unassigned_access(cpu, addr, false, false, 0, size);

        return -1;

    }
@@ -214,6 +215,7 @@ static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size) 
static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size)

{

    TyphoonState *s = opaque;

    CPUState *cs;

    uint64_t ret = 0;



    if (addr & 4) {
@@ -300,7 +302,8 @@ static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size) 
        break;



    default:

        cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);

        cs = CPU(alpha_env_get_cpu(cpu_single_env));

        cpu_unassigned_access(cs, addr, false, false, 0, size);

        return -1;

    }
@@ -312,6 +315,7 @@ static void cchip_write(void *opaque, hwaddr addr, 
                        uint64_t v32, unsigned size)

{

    TyphoonState *s = opaque;

    CPUState *cpu_single_cpu = CPU(alpha_env_get_cpu(cpu_single_env));

    uint64_t val, oldval, newval;



    if (addr & 4) {
@@ -461,7 +465,7 @@ static void cchip_write(void *opaque, hwaddr addr, 
        break;



    default:

        cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);

        cpu_unassigned_access(cpu_single_cpu, addr, true, false, 0, size);

        return;

    }

}
@@ -476,6 +480,7 @@ static void pchip_write(void *opaque, hwaddr addr, 
                        uint64_t v32, unsigned size)

{

    TyphoonState *s = opaque;

    CPUState *cs;

    uint64_t val, oldval;



    if (addr & 4) {
@@ -577,7 +582,8 @@ static void pchip_write(void *opaque, hwaddr addr, 
        break;



    default:

        cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);

        cs = CPU(alpha_env_get_cpu(cpu_single_env));

        cpu_unassigned_access(cs, addr, true, false, 0, size);

        return;

    }

}

include/qom/cpu.h

+33 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 


#include <signal.h>

#include "hw/qdev-core.h"

#include "exec/hwaddr.h"

#include "qemu/thread.h"

#include "qemu/typedefs.h"
@@ -42,12 +43,17 @@ typedef int (*WriteCoreDumpFunction)(void *buf, size_t size, void *opaque); 


typedef struct CPUState CPUState;



typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,

                                    bool is_write, bool is_exec, int opaque,

                                    unsigned size);



/**

 * CPUClass:

 * @class_by_name: Callback to map -cpu command line model name to an

 * instantiatable CPU type.

 * @reset: Callback to reset the #CPUState to its initial state.

 * @do_interrupt: Callback for interrupt handling.

 * @do_unassigned_access: Callback for unassigned access handling.

 * @dump_state: Callback for dumping state.

 * @dump_statistics: Callback for dumping statistics.

 * @get_arch_id: Callback for getting architecture-dependent CPU ID.
@@ -66,6 +72,7 @@ typedef struct CPUClass { 


    void (*reset)(CPUState *cpu);

    void (*do_interrupt)(CPUState *cpu);

    CPUUnassignedAccess do_unassigned_access;

    void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,

                       int flags);

    void (*dump_statistics)(CPUState *cpu, FILE *f,
@@ -280,6 +287,17 @@ static inline void cpu_class_set_vmsd(CPUClass *cc, 
#define cpu_class_set_vmsd(cc, value) ((cc)->vmsd = NULL)

#endif



#ifndef CONFIG_USER_ONLY

static inline void cpu_class_set_do_unassigned_access(CPUClass *cc,

                                                      CPUUnassignedAccess value)

{

    cc->do_unassigned_access = value;

}

#else

#define cpu_class_set_do_unassigned_access(cc, value) \

    ((cc)->do_unassigned_access = NULL)

#endif



/**

 * device_class_set_vmsd:

 * @dc: Device class
@@ -403,6 +421,21 @@ void cpu_interrupt(CPUState *cpu, int mask); 


#endif /* USER_ONLY */



#ifndef CONFIG_USER_ONLY



static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,

                                         bool is_write, bool is_exec,

                                         int opaque, unsigned size)

{

    CPUClass *cc = CPU_GET_CLASS(cpu);



    if (cc->do_unassigned_access) {

        cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);

    }

}



#endif



/**

 * cpu_reset_interrupt:

 * @cpu: The CPU to clear the interrupt on.

memory.c

+8 −6
Original line number Diff line number Diff line
@@ -855,9 +855,10 @@ static uint64_t unassigned_mem_read(void *opaque, hwaddr addr, 
#ifdef DEBUG_UNASSIGNED

    printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);

#endif

#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)

    cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);

#endif

    if (cpu_single_env != NULL) {

        cpu_unassigned_access(ENV_GET_CPU(cpu_single_env),

                              addr, false, false, 0, size);

    }

    return 0;

}
@@ -867,9 +868,10 @@ static void unassigned_mem_write(void *opaque, hwaddr addr, 
#ifdef DEBUG_UNASSIGNED

    printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);

#endif

#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)

    cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);

#endif

    if (cpu_single_env != NULL) {

        cpu_unassigned_access(ENV_GET_CPU(cpu_single_env),

                              addr, true, false, 0, size);

    }

}



static bool unassigned_mem_accepts(void *opaque, hwaddr addr,

target-alpha/cpu.c

+1 −0
Original line number Diff line number Diff line
@@ -263,6 +263,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) 
    cc->class_by_name = alpha_cpu_class_by_name;

    cc->do_interrupt = alpha_cpu_do_interrupt;

    cc->dump_state = alpha_cpu_dump_state;

    cpu_class_set_do_unassigned_access(cc, alpha_cpu_unassigned_access);

    device_class_set_vmsd(dc, &vmstate_alpha_cpu);

}