Commit c647e3fe authored by David Gibson's avatar David Gibson
Browse files

target/ppc: Style fixes for cpu.[ch] 



Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
Reviewed-by: default avatarCédric Le Goater <clg@kaod.org>
Reviewed-by: default avatarGreg Kurz <groug@kaod.org>
parent b93745bb

target/ppc/cpu.h

+129 −108
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ 
#include "qemu-common.h"

#include "qemu/int128.h"



//#define PPC_EMULATE_32BITS_HYPV

/* #define PPC_EMULATE_32BITS_HYPV */



#if defined(TARGET_PPC64)

/* PowerPC 64 definitions */
@@ -32,14 +32,19 @@ 


#define TCG_GUEST_DEFAULT_MO 0



/* Note that the official physical address space bits is 62-M where M

   is implementation dependent.  I've not looked up M for the set of

   cpus we emulate at the system level.  */

/*

 * Note that the official physical address space bits is 62-M where M

 * is implementation dependent.  I've not looked up M for the set of

 * cpus we emulate at the system level.

 */

#define TARGET_PHYS_ADDR_SPACE_BITS 62



/* Note that the PPC environment architecture talks about 80 bit virtual

   addresses, with segmentation.  Obviously that's not all visible to a

   single process, which is all we're concerned with here.  */

/*

 * Note that the PPC environment architecture talks about 80 bit

 * virtual addresses, with segmentation.  Obviously that's not all

 * visible to a single process, which is all we're concerned with

 * here.

 */

#ifdef TARGET_ABI32

# define TARGET_VIRT_ADDR_SPACE_BITS 32

#else
@@ -237,9 +242,11 @@ struct ppc_spr_t { 
    const char *name;

    target_ulong default_value;

#ifdef CONFIG_KVM

    /* We (ab)use the fact that all the SPRs will have ids for the

    /*

     * We (ab)use the fact that all the SPRs will have ids for the

     * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,

     * don't sync this */

     * don't sync this

     */

    uint64_t one_reg_id;

#endif

};
@@ -962,9 +969,10 @@ struct ppc_radix_page_info { 
/*****************************************************************************/

/* The whole PowerPC CPU context */



/* PowerPC needs eight modes for different hypervisor/supervisor/guest +

 * real/paged mode combinations. The other two modes are for external PID

 * load/store.

/*

 * PowerPC needs eight modes for different hypervisor/supervisor/guest

 * + real/paged mode combinations. The other two modes are for

 * external PID load/store.

 */

#define NB_MMU_MODES    10

#define MMU_MODE8_SUFFIX _epl
@@ -976,8 +984,9 @@ struct ppc_radix_page_info { 
#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20



struct CPUPPCState {

    /* First are the most commonly used resources

     * during translated code execution

    /*

     * First are the most commonly used resources during translated

     * code execution

     */

    /* general purpose registers */

    target_ulong gpr[32];
@@ -1023,8 +1032,8 @@ struct CPUPPCState { 
    /* High part of 128-bit helper return.  */

    uint64_t retxh;



    int access_type; /* when a memory exception occurs, the access

                        type is stored here */

    /* when a memory exception occurs, the access type is stored here */

    int access_type;



    CPU_COMMON
@@ -1072,8 +1081,10 @@ struct CPUPPCState { 
    /* SPE registers */

    uint64_t spe_acc;

    uint32_t spe_fscr;

    /* SPE and Altivec can share a status since they will never be used

     * simultaneously */

    /*

     * SPE and Altivec can share a status since they will never be

     * used simultaneously

     */

    float_status vec_status;



    /* Internal devices resources */
@@ -1103,7 +1114,8 @@ struct CPUPPCState { 
    int error_code;

    uint32_t pending_interrupts;

#if !defined(CONFIG_USER_ONLY)

    /* This is the IRQ controller, which is implementation dependent

    /*

     * This is the IRQ controller, which is implementation dependent

     * and only relevant when emulating a complete machine.

     */

    uint32_t irq_input_state;
@@ -1117,7 +1129,8 @@ struct CPUPPCState { 
    hwaddr mpic_iack;

    /* true when the external proxy facility mode is enabled */

    bool mpic_proxy;

    /* set when the processor has an HV mode, thus HV priv

    /*

     * set when the processor has an HV mode, thus HV priv

     * instructions and SPRs are diallowed if MSR:HV is 0

     */

    bool has_hv_mode;
@@ -1149,8 +1162,10 @@ struct CPUPPCState { 


    /* booke timers */



    /* Specifies bit locations of the Time Base used to signal a fixed timer

     * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)

    /*

     * Specifies bit locations of the Time Base used to signal a fixed

     * timer exception on a transition from 0 to 1. (watchdog or

     * fixed-interval timer)

     *

     * 0 selects the least significant bit.

     * 63 selects the most significant bit.
@@ -1290,11 +1305,12 @@ extern const struct VMStateDescription vmstate_ppc_cpu; 


/*****************************************************************************/

void ppc_translate_init(void);

/* you can call this signal handler from your SIGBUS and SIGSEGV

   signal handlers to inform the virtual CPU of exceptions. non zero

   is returned if the signal was handled by the virtual CPU.  */

int cpu_ppc_signal_handler (int host_signum, void *pinfo,

                            void *puc);

/*

 * you can call this signal handler from your SIGBUS and SIGSEGV

 * signal handlers to inform the virtual CPU of exceptions. non zero

 * is returned if the signal was handled by the virtual CPU.

 */

int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc);

#if defined(CONFIG_USER_ONLY)

int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,

                             int mmu_idx);
@@ -1349,7 +1365,8 @@ static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn) 


    gprv = env->gpr[gprn];

    if (env->flags & POWERPC_FLAG_SPE) {

        /* If the CPU implements the SPE extension, we have to get the

        /*

         * If the CPU implements the SPE extension, we have to get the

         * high bits of the GPR from the gprh storage area

         */

        gprv &= 0xFFFFFFFFULL;
@@ -2226,7 +2243,8 @@ enum { 
};



/*****************************************************************************/

/* Memory access type :

/*

 * Memory access type :

 * may be needed for precise access rights control and precise exceptions.

 */

enum {
@@ -2242,7 +2260,8 @@ enum { 
    ACCESS_CACHE = 0x60, /* Cache manipulation               */

};



/* Hardware interruption sources:

/*

 * Hardware interrupt sources:

 *   all those exception can be raised simulteaneously

 */

/* Input pins definitions */
@@ -2325,9 +2344,11 @@ enum { 
enum {

    /* POWER7 input pins */

    POWER7_INPUT_INT        = 0,

    /* POWER7 probably has other inputs, but we don't care about them

    /*

     * POWER7 probably has other inputs, but we don't care about them

     * for any existing machine.  We can wire these up when we need

     * them */

     * them

     */

    POWER7_INPUT_NB,

};