Commit c6138aab authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/rth/tcg-aarch-6-5' into staging 



* remotes/rth/tcg-aarch-6-5: (25 commits)
  tcg-aarch64: Use tcg_out_mov in preference to tcg_out_movr
  tcg-aarch64: Prefer unsigned offsets before signed offsets for ldst
  tcg-aarch64: Introduce tcg_out_insn_3312, _3310, _3313
  tcg-aarch64: Merge aarch64_ldst_get_data/type into tcg_out_op
  tcg-aarch64: Introduce tcg_out_insn_3507
  tcg-aarch64: Support stores of zero
  tcg-aarch64: Implement TCG_TARGET_HAS_new_ldst
  tcg-aarch64: Pass qemu_ld/st arguments directly
  tcg-aarch64: Use TCGMemOp in qemu_ld/st
  tcg-aarch64: Use ADR to pass the return address to the ld/st helpers
  tcg-aarch64: Use tcg_out_call for qemu_ld/st
  tcg-aarch64: Avoid add with zero in tlb load
  tcg-aarch64: Implement tcg_register_jit
  tcg-aarch64: Introduce tcg_out_insn_3314
  tcg-aarch64: Reuse LR in translated code
  tcg-aarch64: Use CBZ and CBNZ
  tcg-aarch64: Create tcg_out_brcond
  tcg-aarch64: Use symbolic names for branches
  tcg-aarch64: Use adrp in tcg_out_movi
  tcg-aarch64: Special case small constants in tcg_out_movi
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 5149e557 b825025f

tcg/aarch64/tcg-target.c

+591 −536

File changed.

Preview size limit exceeded, changes collapsed.

tcg/aarch64/tcg-target.h

+18 −16
Original line number Diff line number Diff line
@@ -17,17 +17,23 @@ 
#undef TCG_TARGET_STACK_GROWSUP



typedef enum {

    TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, TCG_REG_X4,

    TCG_REG_X5, TCG_REG_X6, TCG_REG_X7, TCG_REG_X8, TCG_REG_X9,

    TCG_REG_X10, TCG_REG_X11, TCG_REG_X12, TCG_REG_X13, TCG_REG_X14,

    TCG_REG_X15, TCG_REG_X16, TCG_REG_X17, TCG_REG_X18, TCG_REG_X19,

    TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23, TCG_REG_X24,

    TCG_REG_X25, TCG_REG_X26, TCG_REG_X27, TCG_REG_X28,

    TCG_REG_FP,  /* frame pointer */

    TCG_REG_LR, /* link register */

    TCG_REG_SP,  /* stack pointer or zero register */

    TCG_REG_XZR = TCG_REG_SP /* same register number */

    /* program counter is not directly accessible! */

    TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3,

    TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7,

    TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11,

    TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15,

    TCG_REG_X16, TCG_REG_X17, TCG_REG_X18, TCG_REG_X19,

    TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23,

    TCG_REG_X24, TCG_REG_X25, TCG_REG_X26, TCG_REG_X27,

    TCG_REG_X28, TCG_REG_X29, TCG_REG_X30,



    /* X31 is either the stack pointer or zero, depending on context.  */

    TCG_REG_SP = 31,

    TCG_REG_XZR = 31,



    /* Aliases.  */

    TCG_REG_FP = TCG_REG_X29,

    TCG_REG_LR = TCG_REG_X30,

    TCG_AREG0  = TCG_REG_X19,

} TCGReg;



#define TCG_TARGET_NB_REGS 32
@@ -92,11 +98,7 @@ typedef enum { 
#define TCG_TARGET_HAS_muluh_i64        1

#define TCG_TARGET_HAS_mulsh_i64        1



enum {

    TCG_AREG0 = TCG_REG_X19,

};



#define TCG_TARGET_HAS_new_ldst         0

#define TCG_TARGET_HAS_new_ldst         1



static inline void flush_icache_range(uintptr_t start, uintptr_t stop)

{

user-exec.c

+19 −6
Original line number Diff line number Diff line
@@ -465,16 +465,29 @@ int cpu_signal_handler(int host_signum, void *pinfo, 


#elif defined(__aarch64__)



int cpu_signal_handler(int host_signum, void *pinfo,

                       void *puc)

int cpu_signal_handler(int host_signum, void *pinfo, void *puc)

{

    siginfo_t *info = pinfo;

    struct ucontext *uc = puc;

    uint64_t pc;

    int is_write = 0; /* XXX how to determine? */

    uintptr_t pc = uc->uc_mcontext.pc;

    uint32_t insn = *(uint32_t *)pc;

    bool is_write;



    pc = uc->uc_mcontext.pc;

    return handle_cpu_signal(pc, (uint64_t)info->si_addr,

    /* XXX: need kernel patch to get write flag faster.  */

    is_write = (   (insn & 0xbfff0000) == 0x0c000000   /* C3.3.1 */

                || (insn & 0xbfe00000) == 0x0c800000   /* C3.3.2 */

                || (insn & 0xbfdf0000) == 0x0d000000   /* C3.3.3 */

                || (insn & 0xbfc00000) == 0x0d800000   /* C3.3.4 */

                || (insn & 0x3f400000) == 0x08000000   /* C3.3.6 */

                || (insn & 0x3bc00000) == 0x39000000   /* C3.3.13 */

                || (insn & 0x3fc00000) == 0x3d800000   /* ... 128bit */

                /* Ingore bits 10, 11 & 21, controlling indexing.  */

                || (insn & 0x3bc00000) == 0x38000000   /* C3.3.8-12 */

                || (insn & 0x3fe00000) == 0x3c800000   /* ... 128bit */

                /* Ignore bits 23 & 24, controlling indexing.  */

                || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */



    return handle_cpu_signal(pc, (uintptr_t)info->si_addr,

                             is_write, &uc->uc_sigmask, puc);

}