Commit c51a5cfc authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Make MMFAR banked for v8M 



Make the MMFAR register banked if v8M security extensions are
enabled.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-18-git-send-email-peter.maydell@linaro.org
parent 9d40cd8a

hw/intc/armv7m_nvic.c

+2 −2
Original line number Diff line number Diff line
@@ -506,7 +506,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) 
    case 0xd30: /* Debug Fault Status.  */

        return cpu->env.v7m.dfsr;

    case 0xd34: /* MMFAR MemManage Fault Address */

        return cpu->env.v7m.mmfar;

        return cpu->env.v7m.mmfar[attrs.secure];

    case 0xd38: /* Bus Fault Address.  */

        return cpu->env.v7m.bfar;

    case 0xd3c: /* Aux Fault Status.  */
@@ -720,7 +720,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, 
        cpu->env.v7m.dfsr &= ~value; /* W1C */

        break;

    case 0xd34: /* Mem Manage Address.  */

        cpu->env.v7m.mmfar = value;

        cpu->env.v7m.mmfar[attrs.secure] = value;

        return;

    case 0xd38: /* Bus Fault Address.  */

        cpu->env.v7m.bfar = value;

target/arm/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -427,7 +427,7 @@ typedef struct CPUARMState { 
        uint32_t cfsr; /* Configurable Fault Status */

        uint32_t hfsr; /* HardFault Status */

        uint32_t dfsr; /* Debug Fault Status Register */

        uint32_t mmfar; /* MemManage Fault Address */

        uint32_t mmfar[2]; /* MemManage Fault Address */

        uint32_t bfar; /* BusFault Address */

        unsigned mpu_ctrl[2]; /* MPU_CTRL */

        int exception;

target/arm/helper.c

+2 −2
Original line number Diff line number Diff line
@@ -6375,10 +6375,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) 
            case EXCP_DATA_ABORT:

                env->v7m.cfsr |=

                    (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK);

                env->v7m.mmfar = env->exception.vaddress;

                env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress;

                qemu_log_mask(CPU_LOG_INT,

                              "...with CFSR.DACCVIOL and MMFAR 0x%x\n",

                              env->v7m.mmfar);

                              env->v7m.mmfar[env->v7m.secure]);

                break;

            }

            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);

target/arm/machine.c

+2 −1
Original line number Diff line number Diff line
@@ -121,7 +121,7 @@ static const VMStateDescription vmstate_m = { 
        VMSTATE_UINT32(env.v7m.cfsr, ARMCPU),

        VMSTATE_UINT32(env.v7m.hfsr, ARMCPU),

        VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),

        VMSTATE_UINT32(env.v7m.mmfar, ARMCPU),

        VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU),

        VMSTATE_UINT32(env.v7m.bfar, ARMCPU),

        VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU),

        VMSTATE_INT32(env.v7m.exception, ARMCPU),
@@ -272,6 +272,7 @@ static const VMStateDescription vmstate_m_security = { 
        VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate),

        VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU),

        VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU),

        VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU),

        VMSTATE_END_OF_LIST()

    }

};