Commit c4869ca6 authored by Onur Sahin's avatar Onur Sahin Committed by Peter Maydell
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target-arm: Check undefined opcodes for SWP in A32 decoder 



Make sure we are not treating architecturally Undefined instructions
as a SWP, by verifying the opcodes as per section A8.8.229 of ARMv7-A
specification. Bits [21:20] must be zero for this to be a SWP or SWPB.
We also choose to UNDEF for the architecturally UNPREDICTABLE case of
bits [11:8] not being zero.

Signed-off-by: default avatarOnur Sahin <onursahin08@gmail.com>
[PMM: tweaked commit message]
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 8720daad

target/arm/translate.c

+7 −2
Original line number Diff line number Diff line
@@ -9237,11 +9237,14 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) 
                            }

                        }

                        tcg_temp_free_i32(addr);

                    } else {

                    } else if ((insn & 0x00300f00) == 0) {

                        /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx

                        *  - SWP, SWPB

                        */



                        TCGv taddr;

                        TCGMemOp opc = s->be_data;



                        /* SWP instruction */

                        rm = (insn) & 0xf;



                        if (insn & (1 << 22)) {
@@ -9259,6 +9262,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) 
                                                get_mem_index(s), opc);

                        tcg_temp_free(taddr);

                        store_reg(s, rd, tmp);

                    } else {

                        goto illegal_op;

                    }

                }

            } else {