Commit c47eaf9f authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Compute TB_FLAGS for TBI for user-only 



Enables, but does not turn on, TBI for CONFIG_USER_ONLY.

Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190204132126.3255-4-richard.henderson@linaro.org
[PMM: adjusted #ifdeffery to placate clang, which otherwise complains
about static functions that are unused in the CONFIG_USER_ONLY build]
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 3a471103

target/arm/helper.c

+24 −21
Original line number Diff line number Diff line
@@ -7197,7 +7197,7 @@ uint32_t HELPER(rbit)(uint32_t x) 
    return revbit32(x);

}



#if defined(CONFIG_USER_ONLY)

#ifdef CONFIG_USER_ONLY



/* These should probably raise undefined insn exceptions.  */

void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
@@ -9571,6 +9571,7 @@ void arm_cpu_do_interrupt(CPUState *cs) 
        cs->interrupt_request |= CPU_INTERRUPT_EXITTB;

    }

}

#endif /* !CONFIG_USER_ONLY */



/* Return the exception level which controls this address translation regime */

static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
@@ -9600,6 +9601,8 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) 
    }

}



#ifndef CONFIG_USER_ONLY



/* Return the SCTLR value which controls this address translation regime */

static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)

{
@@ -9655,6 +9658,22 @@ static inline bool regime_translation_big_endian(CPUARMState *env, 
    return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0;

}



/* Return the TTBR associated with this translation regime */

static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,

                                   int ttbrn)

{

    if (mmu_idx == ARMMMUIdx_S2NS) {

        return env->cp15.vttbr_el2;

    }

    if (ttbrn == 0) {

        return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];

    } else {

        return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];

    }

}



#endif /* !CONFIG_USER_ONLY */



/* Return the TCR controlling this translation regime */

static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)

{
@@ -9675,20 +9694,6 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) 
    return mmu_idx;

}



/* Return the TTBR associated with this translation regime */

static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,

                                   int ttbrn)

{

    if (mmu_idx == ARMMMUIdx_S2NS) {

        return env->cp15.vttbr_el2;

    }

    if (ttbrn == 0) {

        return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];

    } else {

        return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];

    }

}



/* Return true if the translation regime is using LPAE format page tables */

static inline bool regime_using_lpae_format(CPUARMState *env,

                                            ARMMMUIdx mmu_idx)
@@ -9714,6 +9719,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) 
    return regime_using_lpae_format(env, mmu_idx);

}



#ifndef CONFIG_USER_ONLY

static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)

{

    switch (mmu_idx) {
@@ -10419,6 +10425,7 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) 


    return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint;

}

#endif /* !CONFIG_USER_ONLY */



ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,

                                        ARMMMUIdx mmu_idx)
@@ -10490,6 +10497,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, 
    return ret;

}



#ifndef CONFIG_USER_ONLY

static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,

                                          ARMMMUIdx mmu_idx)

{
@@ -13746,11 +13754,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 
        *pc = env->pc;

        flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);



#ifndef CONFIG_USER_ONLY

        /*

         * Get control bits for tagged addresses.  Note that the

         * translator only uses this for instruction addresses.

         */

        /* Get control bits for tagged addresses.  */

        {

            ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);

            ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1);
@@ -13769,7 +13773,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 
            flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii);

            flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid);

        }

#endif



        if (cpu_isar_feature(aa64_sve, cpu)) {

            int sve_el = sve_exception_el(env, current_el);

target/arm/internals.h

+0 −21
Original line number Diff line number Diff line
@@ -963,30 +963,9 @@ typedef struct ARMVAParameters { 
    bool using64k   : 1;

} ARMVAParameters;



#ifdef CONFIG_USER_ONLY

static inline ARMVAParameters aa64_va_parameters_both(CPUARMState *env,

                                                      uint64_t va,

                                                      ARMMMUIdx mmu_idx)

{

    return (ARMVAParameters) {

        /* 48-bit address space */

        .tsz = 16,

        /* We can't handle tagged addresses properly in user-only mode */

        .tbi = false,

    };

}



static inline ARMVAParameters aa64_va_parameters(CPUARMState *env,

                                                 uint64_t va,

                                                 ARMMMUIdx mmu_idx, bool data)

{

    return aa64_va_parameters_both(env, va, mmu_idx);

}

#else

ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,

                                        ARMMMUIdx mmu_idx);

ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,

                                   ARMMMUIdx mmu_idx, bool data);

#endif



#endif