Commit c3173a35 authored by Huacai Chen's avatar Huacai Chen Committed by Aleksandar Markovic
Browse files

hw/mips: Add CPU IRQ3 delivery for KVM 



Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add
IP3 delivery as well, because Loongson-3 based machine use both IRQ2
(CPU's IP2) and IRQ3 (CPU's IP3).

Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
Co-developed-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: default avatarAleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: default avatarAleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <1588501221-1205-4-git-send-email-chenhc@lemote.com>
parent aa2953fd

hw/mips/mips_int.c

+1 −1
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) 
        env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));

    }



    if (kvm_enabled() && irq == 2) {

    if (kvm_enabled() && (irq == 2 || irq == 3)) {

        kvm_mips_set_interrupt(cpu, irq, level);

    }