Loading tests/tcg/xtensa/test_mmu.S +207 −14 Original line number Diff line number Diff line Loading @@ -293,26 +293,219 @@ test store_prohibited assert eq, a2, a3 test_end test dtlb_autoload set_vector kernel, 0 movi a2, 0xd4000000 /* Set up page table entry vaddr->paddr, ring=pte_ring, attr=pte_attr * and DTLB way 7 to cover this PTE, ring=pt_ring, attr=pt_attr */ .macro pt_setup pt_ring, pt_attr, pte_ring, vaddr, paddr, pte_attr movi a2, 0x80000000 wsr a2, ptevaddr movi a3, 0x00001013 s32i a3, a2, 4 movi a3, 0x80000007 | (((\vaddr) >> 10) & 0xfffff000) /* way 7 */ movi a4, 0x04000003 | ((\pt_ring) << 4) /* PADDR 64M */ wdtlb a4, a3 isync movi a3, ((\paddr) & 0xfffff000) | ((\pte_ring) << 4) | (\pte_attr) movi a1, ((\vaddr) >> 12) << 2 add a2, a1, a2 s32i a3, a2, 0 movi a3, 0x80000007 | (((\vaddr) >> 10) & 0xfffff000) /* way 7 */ movi a4, 0x04000000 | ((\pt_ring) << 4) | (\pt_attr) /* PADDR 64M */ wdtlb a4, a3 isync movi a3, (\vaddr) .endm /* out: PS.RING=ring, PS.EXCM=excm, a3=vaddr */ .macro go_ring ring, excm, vaddr movi a3, 10f pitlb a3, a3 ritlb1 a2, a3 movi a1, 0x10 or a2, a2, a1 movi a1, 0x000ff000 and a3, a3, a1 movi a1, 4 or a3, a3, a1 witlb a2, a3 movi a3, 10f movi a1, 0x000fffff and a1, a3, a1 movi a2, 0 wsr a2, excvaddr movi a3, \vaddr movi a2, 0x4000f | ((\ring) << 6) | ((\excm) << 4) jx a1 10: wsr a2, ps isync .endm /* in: a3 -- virtual address to test */ .macro assert_auto_tlb movi a2, 0x4000f wsr a2, ps isync pdtlb a2, a3 movi a1, 0xfffff01f and a2, a2, a1 movi a1, 0xfffff000 and a1, a1, a3 xor a1, a1, a2 assert gei, a1, 0x10 movi a2, 0x14 assert lt, a1, a2 .endm /* in: a3 -- virtual address to test */ .macro assert_no_auto_tlb movi a2, 0x4000f wsr a2, ps isync pdtlb a2, a3 movi a1, 0x10 and a1, a1, a2 assert eqi, a1, 0 l8ui a1, a3, 0 pdtlb a2, a3 movi a1, 0xfffff010 and a1, a1, a2 movi a3, 0x00001010 assert eq, a1, a3 movi a1, 0xf .endm .macro assert_sr sr, v rsr a2, \sr movi a1, (\v) assert eq, a1, a2 .endm .macro assert_epc1_1m vaddr movi a2, (\vaddr) movi a1, 0xfffff and a1, a1, a2 assert lti, a1, 4 rsr a2, epc1 assert eq, a1, a2 .endm test dtlb_autoload set_vector kernel, 0 pt_setup 0, 3, 1, 0x1000, 0x1000, 3 assert_no_auto_tlb l8ui a1, a3, 0 rsr a2, excvaddr assert eq, a2, a3 assert_auto_tlb test_end test autoload_load_store_privilege set_vector kernel, 0 set_vector double, 2f pt_setup 0, 3, 0, 0x2000, 0x2000, 3 movi a3, 0x2004 assert_no_auto_tlb movi a2, 0x4005f /* ring 1 + excm => cring == 0 */ wsr a2, ps isync 1: l32e a2, a3, -4 /* ring used */ test_fail 2: rsr a2, excvaddr addi a1, a3, -4 assert eq, a1, a2 assert_auto_tlb assert_sr depc, 1b assert_sr exccause, 26 test_end test autoload_pte_load_prohibited set_vector kernel, 2f pt_setup 0, 3, 0, 0x3000, 0, 0xc assert_no_auto_tlb 1: l32i a2, a3, 0 test_fail 2: rsr a2, excvaddr assert eq, a2, a3 assert_auto_tlb assert_sr epc1, 1b assert_sr exccause, 28 test_end test autoload_pt_load_prohibited set_vector kernel, 2f pt_setup 0, 0xc, 0, 0x4000, 0x4000, 3 assert_no_auto_tlb 1: l32i a2, a3, 0 test_fail 2: rsr a2, excvaddr assert eq, a2, a3 assert_no_auto_tlb assert_sr epc1, 1b assert_sr exccause, 24 test_end test autoload_pt_privilege set_vector kernel, 2f pt_setup 0, 3, 1, 0x5000, 0, 3 go_ring 1, 0, 0x5001 l8ui a2, a3, 0 1: syscall 2: rsr a2, excvaddr assert eq, a2, a3 assert_auto_tlb assert_epc1_1m 1b assert_sr exccause, 1 test_end test autoload_pte_privilege set_vector kernel, 2f pt_setup 0, 3, 0, 0x6000, 0, 3 go_ring 1, 0, 0x6001 1: l8ui a2, a3, 0 syscall 2: rsr a2, excvaddr assert eq, a2, a3 assert_auto_tlb assert_epc1_1m 1b assert_sr exccause, 26 test_end test autoload_3_level_pt set_vector kernel, 2f pt_setup 1, 3, 1, 0x00400000, 0, 3 pt_setup 1, 3, 1, 0x80001000, 0x2000000, 3 go_ring 1, 0, 0x00400001 1: l8ui a2, a3, 0 syscall 2: rsr a2, excvaddr assert eq, a2, a3 assert_no_auto_tlb assert_epc1_1m 1b assert_sr exccause, 24 test_end test_suite_end Loading
tests/tcg/xtensa/test_mmu.S +207 −14 Original line number Diff line number Diff line Loading @@ -293,26 +293,219 @@ test store_prohibited assert eq, a2, a3 test_end test dtlb_autoload set_vector kernel, 0 movi a2, 0xd4000000 /* Set up page table entry vaddr->paddr, ring=pte_ring, attr=pte_attr * and DTLB way 7 to cover this PTE, ring=pt_ring, attr=pt_attr */ .macro pt_setup pt_ring, pt_attr, pte_ring, vaddr, paddr, pte_attr movi a2, 0x80000000 wsr a2, ptevaddr movi a3, 0x00001013 s32i a3, a2, 4 movi a3, 0x80000007 | (((\vaddr) >> 10) & 0xfffff000) /* way 7 */ movi a4, 0x04000003 | ((\pt_ring) << 4) /* PADDR 64M */ wdtlb a4, a3 isync movi a3, ((\paddr) & 0xfffff000) | ((\pte_ring) << 4) | (\pte_attr) movi a1, ((\vaddr) >> 12) << 2 add a2, a1, a2 s32i a3, a2, 0 movi a3, 0x80000007 | (((\vaddr) >> 10) & 0xfffff000) /* way 7 */ movi a4, 0x04000000 | ((\pt_ring) << 4) | (\pt_attr) /* PADDR 64M */ wdtlb a4, a3 isync movi a3, (\vaddr) .endm /* out: PS.RING=ring, PS.EXCM=excm, a3=vaddr */ .macro go_ring ring, excm, vaddr movi a3, 10f pitlb a3, a3 ritlb1 a2, a3 movi a1, 0x10 or a2, a2, a1 movi a1, 0x000ff000 and a3, a3, a1 movi a1, 4 or a3, a3, a1 witlb a2, a3 movi a3, 10f movi a1, 0x000fffff and a1, a3, a1 movi a2, 0 wsr a2, excvaddr movi a3, \vaddr movi a2, 0x4000f | ((\ring) << 6) | ((\excm) << 4) jx a1 10: wsr a2, ps isync .endm /* in: a3 -- virtual address to test */ .macro assert_auto_tlb movi a2, 0x4000f wsr a2, ps isync pdtlb a2, a3 movi a1, 0xfffff01f and a2, a2, a1 movi a1, 0xfffff000 and a1, a1, a3 xor a1, a1, a2 assert gei, a1, 0x10 movi a2, 0x14 assert lt, a1, a2 .endm /* in: a3 -- virtual address to test */ .macro assert_no_auto_tlb movi a2, 0x4000f wsr a2, ps isync pdtlb a2, a3 movi a1, 0x10 and a1, a1, a2 assert eqi, a1, 0 l8ui a1, a3, 0 pdtlb a2, a3 movi a1, 0xfffff010 and a1, a1, a2 movi a3, 0x00001010 assert eq, a1, a3 movi a1, 0xf .endm .macro assert_sr sr, v rsr a2, \sr movi a1, (\v) assert eq, a1, a2 .endm .macro assert_epc1_1m vaddr movi a2, (\vaddr) movi a1, 0xfffff and a1, a1, a2 assert lti, a1, 4 rsr a2, epc1 assert eq, a1, a2 .endm test dtlb_autoload set_vector kernel, 0 pt_setup 0, 3, 1, 0x1000, 0x1000, 3 assert_no_auto_tlb l8ui a1, a3, 0 rsr a2, excvaddr assert eq, a2, a3 assert_auto_tlb test_end test autoload_load_store_privilege set_vector kernel, 0 set_vector double, 2f pt_setup 0, 3, 0, 0x2000, 0x2000, 3 movi a3, 0x2004 assert_no_auto_tlb movi a2, 0x4005f /* ring 1 + excm => cring == 0 */ wsr a2, ps isync 1: l32e a2, a3, -4 /* ring used */ test_fail 2: rsr a2, excvaddr addi a1, a3, -4 assert eq, a1, a2 assert_auto_tlb assert_sr depc, 1b assert_sr exccause, 26 test_end test autoload_pte_load_prohibited set_vector kernel, 2f pt_setup 0, 3, 0, 0x3000, 0, 0xc assert_no_auto_tlb 1: l32i a2, a3, 0 test_fail 2: rsr a2, excvaddr assert eq, a2, a3 assert_auto_tlb assert_sr epc1, 1b assert_sr exccause, 28 test_end test autoload_pt_load_prohibited set_vector kernel, 2f pt_setup 0, 0xc, 0, 0x4000, 0x4000, 3 assert_no_auto_tlb 1: l32i a2, a3, 0 test_fail 2: rsr a2, excvaddr assert eq, a2, a3 assert_no_auto_tlb assert_sr epc1, 1b assert_sr exccause, 24 test_end test autoload_pt_privilege set_vector kernel, 2f pt_setup 0, 3, 1, 0x5000, 0, 3 go_ring 1, 0, 0x5001 l8ui a2, a3, 0 1: syscall 2: rsr a2, excvaddr assert eq, a2, a3 assert_auto_tlb assert_epc1_1m 1b assert_sr exccause, 1 test_end test autoload_pte_privilege set_vector kernel, 2f pt_setup 0, 3, 0, 0x6000, 0, 3 go_ring 1, 0, 0x6001 1: l8ui a2, a3, 0 syscall 2: rsr a2, excvaddr assert eq, a2, a3 assert_auto_tlb assert_epc1_1m 1b assert_sr exccause, 26 test_end test autoload_3_level_pt set_vector kernel, 2f pt_setup 1, 3, 1, 0x00400000, 0, 3 pt_setup 1, 3, 1, 0x80001000, 0x2000000, 3 go_ring 1, 0, 0x00400001 1: l8ui a2, a3, 0 syscall 2: rsr a2, excvaddr assert eq, a2, a3 assert_no_auto_tlb assert_epc1_1m 1b assert_sr exccause, 24 test_end test_suite_end