Commit bfc2455d authored by Liu, Jinsong's avatar Liu, Jinsong Committed by Marcelo Tosatti
Browse files

kvm: support TSC deadline MSR 



KVM add emulation of lapic tsc deadline timer for guest.
This patch is co-operation work at qemu side.

Signed-off-by: default avatarLiu, Jinsong <jinsong.liu@intel.com>
Signed-off-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
parent d11cf8cc

target-i386/cpu.h

+3 −1
Original line number Diff line number Diff line
@@ -283,6 +283,7 @@ 
#define MSR_IA32_APICBASE_BSP           (1<<8)

#define MSR_IA32_APICBASE_ENABLE        (1<<11)

#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)

#define MSR_IA32_TSCDEADLINE            0x6e0



#define MSR_MTRRcap			0xfe

#define MSR_MTRRcap_VCNT		8
@@ -687,6 +688,7 @@ typedef struct CPUX86State { 
    uint64_t async_pf_en_msr;



    uint64_t tsc;

    uint64_t tsc_deadline;



    uint64_t mcg_status;
@@ -947,7 +949,7 @@ uint64_t cpu_get_tsc(CPUX86State *env); 
#define cpu_list_id x86_cpu_list

#define cpudef_setup	x86_cpudef_setup



#define CPU_SAVE_VERSION 12

#define CPU_SAVE_VERSION 13



/* MMU modes definitions */

#define MMU_MODE0_SUFFIX _kernel

target-i386/kvm.c

+14 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 


static bool has_msr_star;

static bool has_msr_hsave_pa;

static bool has_msr_tsc_deadline;

static bool has_msr_async_pf_en;

static int lm_capable_kernel;
@@ -568,6 +569,10 @@ static int kvm_get_supported_msrs(KVMState *s) 
                    has_msr_hsave_pa = true;

                    continue;

                }

                if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {

                    has_msr_tsc_deadline = true;

                    continue;

                }

            }

        }
@@ -881,6 +886,9 @@ static int kvm_put_msrs(CPUState *env, int level) 
    if (has_msr_hsave_pa) {

        kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);

    }

    if (has_msr_tsc_deadline) {

        kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);

    }

#ifdef TARGET_X86_64

    if (lm_capable_kernel) {

        kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
@@ -1127,6 +1135,9 @@ static int kvm_get_msrs(CPUState *env) 
    if (has_msr_hsave_pa) {

        msrs[n++].index = MSR_VM_HSAVE_PA;

    }

    if (has_msr_tsc_deadline) {

        msrs[n++].index = MSR_IA32_TSCDEADLINE;

    }



    if (!env->tsc_valid) {

        msrs[n++].index = MSR_IA32_TSC;
@@ -1195,6 +1206,9 @@ static int kvm_get_msrs(CPUState *env) 
        case MSR_IA32_TSC:

            env->tsc = msrs[i].data;

            break;

        case MSR_IA32_TSCDEADLINE:

            env->tsc_deadline = msrs[i].data;

            break;

        case MSR_VM_HSAVE_PA:

            env->vm_hsave = msrs[i].data;

            break;

target-i386/machine.c

+1 −0
Original line number Diff line number Diff line
@@ -410,6 +410,7 @@ static const VMStateDescription vmstate_cpu = { 
        VMSTATE_UINT64_V(xcr0, CPUState, 12),

        VMSTATE_UINT64_V(xstate_bv, CPUState, 12),

        VMSTATE_YMMH_REGS_VARS(ymmh_regs, CPUState, CPU_NB_REGS, 12),

        VMSTATE_UINT64_V(tsc_deadline, CPUState, 13),

        VMSTATE_END_OF_LIST()

        /* The above list is not sorted /wrt version numbers, watch out! */

    },