Commit bf13bfab authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

i386: implement IGNNE 



Change the handling of port F0h writes and FPU exceptions to implement IGNNE.

The implementation mixes a bit what the chipset and processor do in real
hardware, but the effect is the same as what happens with actual FERR#
and IGNNE# pins: writing to port F0h asserts IGNNE# in addition to lowering
FP_IRQ; while clearing the SE bit in the FPU status word deasserts IGNNE#.

Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 5caa1833

hw/i386/pc.c

+1 −1
Original line number Diff line number Diff line
@@ -385,7 +385,7 @@ static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 
                           unsigned size)

{

    if (tcg_enabled()) {

        cpu_clear_ferr();

        cpu_set_ignne();

    }

}

target/i386/cpu.h

+3 −1
Original line number Diff line number Diff line
@@ -203,6 +203,7 @@ typedef enum X86Seg { 
#define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */

#define HF2_MPX_PR_SHIFT         5 /* BNDCFGx.BNDPRESERVE */

#define HF2_NPT_SHIFT            6 /* Nested Paging enabled */

#define HF2_IGNNE_SHIFT          7 /* Ignore CR0.NE=0 */



#define HF2_GIF_MASK            (1 << HF2_GIF_SHIFT)

#define HF2_HIF_MASK            (1 << HF2_HIF_SHIFT)
@@ -211,6 +212,7 @@ typedef enum X86Seg { 
#define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)

#define HF2_MPX_PR_MASK         (1 << HF2_MPX_PR_SHIFT)

#define HF2_NPT_MASK            (1 << HF2_NPT_SHIFT)

#define HF2_IGNNE_MASK          (1 << HF2_IGNNE_SHIFT)



#define CR0_PE_SHIFT 0

#define CR0_MP_SHIFT 1
@@ -1762,7 +1764,7 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env); 
int cpu_get_pic_interrupt(CPUX86State *s);

/* MSDOS compatibility mode FPU exception support */

void x86_register_ferr_irq(qemu_irq irq);

void cpu_clear_ferr(void);

void cpu_set_ignne(void);

/* mpx_helper.c */

void cpu_sync_bndcs_hflags(CPUX86State *env);

target/i386/fpu_helper.c

+27 −7
Original line number Diff line number Diff line
@@ -70,14 +70,24 @@ void x86_register_ferr_irq(qemu_irq irq) 
    ferr_irq = irq;

}



void cpu_clear_ferr(void)

static void cpu_clear_ignne(void)

{

    qemu_irq_lower(ferr_irq);

    CPUX86State *env = &X86_CPU(first_cpu)->env;

    env->hflags2 &= ~HF2_IGNNE_MASK;

}



static void cpu_set_ferr(void)

void cpu_set_ignne(void)

{

    qemu_irq_raise(ferr_irq);

    CPUX86State *env = &X86_CPU(first_cpu)->env;

    env->hflags2 |= HF2_IGNNE_MASK;

    /*

     * We get here in response to a write to port F0h.  The chipset should

     * deassert FP_IRQ and FERR# instead should stay signaled until FPSW_SE is

     * cleared, because FERR# and FP_IRQ are two separate pins on real

     * hardware.  However, we don't model FERR# as a qemu_irq, so we just

     * do directly what the chipset would do, i.e. deassert FP_IRQ.

     */

    qemu_irq_lower(ferr_irq);

}

#endif
@@ -160,8 +170,8 @@ static void fpu_raise_exception(CPUX86State *env, uintptr_t retaddr) 
        raise_exception_ra(env, EXCP10_COPR, retaddr);

    }

#if !defined(CONFIG_USER_ONLY)

    else {

        cpu_set_ferr();

    else if (ferr_irq && !(env->hflags2 & HF2_IGNNE_MASK)) {

        qemu_irq_raise(ferr_irq);

    }

#endif

}
@@ -1056,7 +1066,17 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32) 
static void cpu_set_fpus(CPUX86State *env, uint16_t fpus)

{

    env->fpstt = (fpus >> 11) & 7;

    env->fpus = fpus & ~0x3800;

    env->fpus = fpus & ~0x3800 & ~FPUS_B;

    env->fpus |= env->fpus & FPUS_SE ? FPUS_B : 0;

#if !defined(CONFIG_USER_ONLY)

    if (!(env->fpus & FPUS_SE)) {

        /*

         * Here the processor deasserts FERR#; in response, the chipset deasserts

         * IGNNE#.

         */

        cpu_clear_ignne();

    }

#endif

}



static void do_fldenv(CPUX86State *env, target_ulong ptr, int data32,