Commit becdfa00 authored by Marc-André Lureau's avatar Marc-André Lureau Committed by Paolo Bonzini
Browse files

char: replace PROP_CHR with CharBackend 



Store the property in a CharBackend instead of CharDriverState*.  This
also replace systematically chr by chr.chr to access the
CharDriverState*. The following patches will replace it with calls to
qemu_chr_fe CharBackend functions.

Signed-off-by: default avatarMarc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20161022095318.17775-12-marcandre.lureau@redhat.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent ecb672d1

hw/arm/pxa2xx.c

+10 −8
Original line number Diff line number Diff line
@@ -1764,7 +1764,7 @@ struct PXA2xxFIrState { 
    qemu_irq rx_dma;

    qemu_irq tx_dma;

    uint32_t enable;

    CharDriverState *chr;

    CharBackend chr;



    uint8_t control[3];

    uint8_t status[2];
@@ -1898,14 +1898,16 @@ static void pxa2xx_fir_write(void *opaque, hwaddr addr, 
        pxa2xx_fir_update(s);

        break;

    case ICDR:

        if (s->control[2] & (1 << 2))			/* TXP */

        if (s->control[2] & (1 << 2)) { /* TXP */

            ch = value;

        else

        } else {

            ch = ~value;

        if (s->chr && s->enable && (s->control[0] & (1 << 3)))	/* TXE */

        }

        if (s->chr.chr && s->enable && (s->control[0] & (1 << 3))) { /* TXE */

            /* XXX this blocks entire thread. Rewrite to use

             * qemu_chr_fe_write and background I/O callbacks */

            qemu_chr_fe_write_all(s->chr, &ch, 1);

            qemu_chr_fe_write_all(s->chr.chr, &ch, 1);

        }

        break;

    case ICSR0:

        s->status[0] &= ~(value & 0x66);
@@ -1973,9 +1975,9 @@ static void pxa2xx_fir_realize(DeviceState *dev, Error **errp) 
{

    PXA2xxFIrState *s = PXA2XX_FIR(dev);



    if (s->chr) {

        qemu_chr_fe_claim_no_fail(s->chr);

        qemu_chr_add_handlers(s->chr, pxa2xx_fir_is_empty,

    if (s->chr.chr) {

        qemu_chr_fe_claim_no_fail(s->chr.chr);

        qemu_chr_add_handlers(s->chr.chr, pxa2xx_fir_is_empty,

                        pxa2xx_fir_rx, pxa2xx_fir_event, s);

    }

}

hw/arm/strongarm.c

+7 −7
Original line number Diff line number Diff line
@@ -912,7 +912,7 @@ typedef struct StrongARMUARTState { 
    SysBusDevice parent_obj;



    MemoryRegion iomem;

    CharDriverState *chr;

    CharBackend chr;

    qemu_irq irq;



    uint8_t utcr0;
@@ -1020,8 +1020,8 @@ static void strongarm_uart_update_parameters(StrongARMUARTState *s) 
    ssp.data_bits = data_bits;

    ssp.stop_bits = stop_bits;

    s->char_transmit_time =  (NANOSECONDS_PER_SECOND / speed) * frame_size;

    if (s->chr) {

        qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);

    if (s->chr.chr) {

        qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);

    }



    DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
@@ -1107,10 +1107,10 @@ static void strongarm_uart_tx(void *opaque) 


    if (s->utcr3 & UTCR3_LBM) /* loopback */ {

        strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);

    } else if (s->chr) {

    } else if (s->chr.chr) {

        /* XXX this blocks entire thread. Rewrite to use

         * qemu_chr_fe_write and background I/O callbacks */

        qemu_chr_fe_write_all(s->chr, &s->tx_fifo[s->tx_start], 1);

        qemu_chr_fe_write_all(s->chr.chr, &s->tx_fifo[s->tx_start], 1);

    }



    s->tx_start = (s->tx_start + 1) % 8;
@@ -1239,8 +1239,8 @@ static void strongarm_uart_init(Object *obj) 
    s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s);

    s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s);



    if (s->chr) {

        qemu_chr_add_handlers(s->chr,

    if (s->chr.chr) {

        qemu_chr_add_handlers(s->chr.chr,

                        strongarm_uart_can_receive,

                        strongarm_uart_receive,

                        strongarm_uart_event,

hw/char/bcm2835_aux.c

+6 −6
Original line number Diff line number Diff line
@@ -79,8 +79,8 @@ static uint64_t bcm2835_aux_read(void *opaque, hwaddr offset, unsigned size) 
                s->read_pos = 0;

            }

        }

        if (s->chr) {

            qemu_chr_accept_input(s->chr);

        if (s->chr.chr) {

            qemu_chr_accept_input(s->chr.chr);

        }

        bcm2835_aux_update(s);

        return c;
@@ -168,10 +168,10 @@ static void bcm2835_aux_write(void *opaque, hwaddr offset, uint64_t value, 
    case AUX_MU_IO_REG:

        /* "DLAB bit set means access baudrate register" is NYI */

        ch = value;

        if (s->chr) {

        if (s->chr.chr) {

            /* XXX this blocks entire thread. Rewrite to use

             * qemu_chr_fe_write and background I/O callbacks */

            qemu_chr_fe_write_all(s->chr, &ch, 1);

            qemu_chr_fe_write_all(s->chr.chr, &ch, 1);

        }

        break;
@@ -282,8 +282,8 @@ static void bcm2835_aux_realize(DeviceState *dev, Error **errp) 
{

    BCM2835AuxState *s = BCM2835_AUX(dev);



    if (s->chr) {

        qemu_chr_add_handlers(s->chr, bcm2835_aux_can_receive,

    if (s->chr.chr) {

        qemu_chr_add_handlers(s->chr.chr, bcm2835_aux_can_receive,

                              bcm2835_aux_receive, NULL, s);

    }

}

hw/char/cadence_uart.c

+13 −13
Original line number Diff line number Diff line
@@ -142,8 +142,8 @@ static void uart_rx_reset(CadenceUARTState *s) 
{

    s->rx_wpos = 0;

    s->rx_count = 0;

    if (s->chr) {

        qemu_chr_accept_input(s->chr);

    if (s->chr.chr) {

        qemu_chr_accept_input(s->chr.chr);

    }

}
@@ -156,8 +156,8 @@ static void uart_send_breaks(CadenceUARTState *s) 
{

    int break_enabled = 1;



    if (s->chr) {

        qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,

    if (s->chr.chr) {

        qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_SERIAL_SET_BREAK,

                                   &break_enabled);

    }

}
@@ -210,8 +210,8 @@ static void uart_parameters_setup(CadenceUARTState *s) 


    packet_size += ssp.data_bits + ssp.stop_bits;

    s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;

    if (s->chr) {

        qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);

    if (s->chr.chr) {

        qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);

    }

}
@@ -278,7 +278,7 @@ static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond, 
    int ret;



    /* instant drain the fifo when there's no back-end */

    if (!s->chr) {

    if (!s->chr.chr) {

        s->tx_count = 0;

        return FALSE;

    }
@@ -287,7 +287,7 @@ static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond, 
        return FALSE;

    }



    ret = qemu_chr_fe_write(s->chr, s->tx_fifo, s->tx_count);

    ret = qemu_chr_fe_write(s->chr.chr, s->tx_fifo, s->tx_count);



    if (ret >= 0) {

        s->tx_count -= ret;
@@ -295,7 +295,7 @@ static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond, 
    }



    if (s->tx_count) {

        guint r = qemu_chr_fe_add_watch(s->chr, G_IO_OUT|G_IO_HUP,

        guint r = qemu_chr_fe_add_watch(s->chr.chr, G_IO_OUT | G_IO_HUP,

                                        cadence_uart_xmit, s);

        if (!r) {

            s->tx_count = 0;
@@ -368,8 +368,8 @@ static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c) 
        *c = s->rx_fifo[rx_rpos];

        s->rx_count--;



        if (s->chr) {

            qemu_chr_accept_input(s->chr);

        if (s->chr.chr) {

            qemu_chr_accept_input(s->chr.chr);

        }

    } else {

        *c = 0;
@@ -474,8 +474,8 @@ static void cadence_uart_realize(DeviceState *dev, Error **errp) 
    s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,

                                          fifo_trigger_update, s);



    if (s->chr) {

        qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,

    if (s->chr.chr) {

        qemu_chr_add_handlers(s->chr.chr, uart_can_receive, uart_receive,

                              uart_event, s);

    }

}

hw/char/debugcon.c

+4 −4
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ 


typedef struct DebugconState {

    MemoryRegion io;

    CharDriverState *chr;

    CharBackend chr;

    uint32_t readback;

} DebugconState;
@@ -62,7 +62,7 @@ static void debugcon_ioport_write(void *opaque, hwaddr addr, uint64_t val, 


    /* XXX this blocks entire thread. Rewrite to use

     * qemu_chr_fe_write and background I/O callbacks */

    qemu_chr_fe_write_all(s->chr, &ch, 1);

    qemu_chr_fe_write_all(s->chr.chr, &ch, 1);

}
@@ -87,12 +87,12 @@ static const MemoryRegionOps debugcon_ops = { 


static void debugcon_realize_core(DebugconState *s, Error **errp)

{

    if (!s->chr) {

    if (!s->chr.chr) {

        error_setg(errp, "Can't create debugcon device, empty char device");

        return;

    }



    qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, s);

    qemu_chr_add_handlers(s->chr.chr, NULL, NULL, NULL, s);

}



static void debugcon_isa_realizefn(DeviceState *dev, Error **errp)