Commit becb6667 authored by Paolo Bonzini's avatar Paolo Bonzini Committed by Eduardo Habkost
Browse files

target-i386: add ABM to Haswell* and Broadwell* CPU models 



ABM is only implemented as a single instruction set by AMD; all AMD
processors support both instructions or neither. Intel considers POPCNT
as part of SSE4.2, and LZCNT as part of BMI1, but Intel also uses AMD's
ABM flag to indicate support for both POPCNT and LZCNT.  It has to be
added to Haswell and Broadwell because Haswell, by adding LZCNT, has
completed the ABM.

Tested with "qemu-kvm -cpu Haswell-noTSX,enforce" (and also with older
machine types) on an Haswell-EP machine.

Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
Reviewed-by: default avatarEduardo Habkost <ehabkost@redhat.com>
Signed-off-by: default avatarEduardo Habkost <ehabkost@redhat.com>
parent c9b8f6b6

include/hw/i386/pc.h

+21 −1
Original line number Diff line number Diff line
@@ -298,7 +298,27 @@ int e820_get_num_entries(void); 
bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);



#define PC_COMPAT_2_4 \

        HW_COMPAT_2_4

        HW_COMPAT_2_4 \

        {\

            .driver   = "Haswell-" TYPE_X86_CPU,\

            .property = "abm",\

            .value    = "off",\

        },\

        {\

            .driver   = "Haswell-noTSX-" TYPE_X86_CPU,\

            .property = "abm",\

            .value    = "off",\

        },\

        {\

            .driver   = "Broadwell-" TYPE_X86_CPU,\

            .property = "abm",\

            .value    = "off",\

        },\

        {\

            .driver   = "Broadwell-noTSX-" TYPE_X86_CPU,\

            .property = "abm",\

            .value    = "off",\

        },



#define PC_COMPAT_2_3 \

        PC_COMPAT_2_4 \

target-i386/cpu.c

+4 −4
Original line number Diff line number Diff line
@@ -1081,7 +1081,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |

            CPUID_EXT2_SYSCALL,

        .features[FEAT_8000_0001_ECX] =

            CPUID_EXT3_LAHF_LM,

            CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,

        .features[FEAT_7_0_EBX] =

            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |

            CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
@@ -1116,7 +1116,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |

            CPUID_EXT2_SYSCALL,

        .features[FEAT_8000_0001_ECX] =

            CPUID_EXT3_LAHF_LM,

            CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,

        .features[FEAT_7_0_EBX] =

            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |

            CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
@@ -1153,7 +1153,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |

            CPUID_EXT2_SYSCALL,

        .features[FEAT_8000_0001_ECX] =

            CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,

            CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,

        .features[FEAT_7_0_EBX] =

            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |

            CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
@@ -1191,7 +1191,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |

            CPUID_EXT2_SYSCALL,

        .features[FEAT_8000_0001_ECX] =

            CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,

            CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,

        .features[FEAT_7_0_EBX] =

            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |

            CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |