Commit be1f13ac authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150813' into staging 



MIPS patches 2015-08-13

Changes:
* mips32r5-generic CPU updated and renamed to P5600
* improvements in LWL/LDL, logging and fulong2e

# gpg: Signature made Thu 13 Aug 2015 17:10:59 BST using RSA key ID 0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4  4FC0 5211 8E3C 0B29 DA6B

* remotes/lalrae/tags/mips-20150813:
  target-mips: Use CPU_LOG_INT for logging related to interrupts
  hw/pci-host/bonito: Avoid buffer overrun for bad LDMA/COP accesses
  target-mips: simplify LWL/LDL mask generation
  target-mips: update mips32r5-generic into P5600

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 5c314a2e c8557016

hw/pci-host/bonito.c

+16 −0
Original line number Diff line number Diff line
@@ -355,6 +355,10 @@ static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr, 
    uint32_t val;

    PCIBonitoState *s = opaque;



    if (addr >= sizeof(s->bonldma)) {

        return 0;

    }



    val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)];



    return val;
@@ -365,6 +369,10 @@ static void bonito_ldma_writel(void *opaque, hwaddr addr, 
{

    PCIBonitoState *s = opaque;



    if (addr >= sizeof(s->bonldma)) {

        return;

    }



    ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff;

}
@@ -384,6 +392,10 @@ static uint64_t bonito_cop_readl(void *opaque, hwaddr addr, 
    uint32_t val;

    PCIBonitoState *s = opaque;



    if (addr >= sizeof(s->boncop)) {

        return 0;

    }



    val = ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)];



    return val;
@@ -394,6 +406,10 @@ static void bonito_cop_writel(void *opaque, hwaddr addr, 
{

    PCIBonitoState *s = opaque;



    if (addr >= sizeof(s->boncop)) {

        return;

    }



    ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff;

}

target-mips/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -395,7 +395,7 @@ struct CPUMIPSState { 
#define CP0C0_K23  28

#define CP0C0_KU   25

#define CP0C0_MDU  20

#define CP0C0_MM   17

#define CP0C0_MM   18

#define CP0C0_BM   16

#define CP0C0_BE   15

#define CP0C0_AT   13

target-mips/helper.c

+11 −19
Original line number Diff line number Diff line
@@ -127,10 +127,6 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, 
    /* effective address (modified for KVM T&E kernel segments) */

    target_ulong address = real_address;



#if 0

    qemu_log("user mode %d h %08x\n", user_mode, env->hflags);

#endif



#define USEG_LIMIT      0x7FFFFFFFUL

#define KSEG0_BASE      0x80000000UL

#define KSEG1_BASE      0xA0000000UL
@@ -227,11 +223,6 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, 
            ret = TLBRET_BADADDR;

        }

    }

#if 0

    qemu_log(TARGET_FMT_lx " %d %d => %" HWADDR_PRIx " %d (%d)\n",

            address, rw, access_type, *physical, *prot, ret);

#endif



    return ret;

}

#endif
@@ -487,14 +478,16 @@ void mips_cpu_do_interrupt(CPUState *cs) 
    int cause = -1;

    const char *name;



    if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {

    if (qemu_loglevel_mask(CPU_LOG_INT)

        && cs->exception_index != EXCP_EXT_INTERRUPT) {

        if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {

            name = "unknown";

        } else {

            name = excp_names[cs->exception_index];

        }



        qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",

        qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx

                 " %s exception\n",

                 __func__, env->active_tc.PC, env->CP0_EPC, name);

    }

    if (cs->exception_index == EXCP_EXT_INTERRUPT &&
@@ -747,11 +740,10 @@ void mips_cpu_do_interrupt(CPUState *cs) 
        env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);

        break;

    default:

        qemu_log("Invalid MIPS exception %d. Exiting\n", cs->exception_index);

        printf("Invalid MIPS exception %d. Exiting\n", cs->exception_index);

        exit(1);

        abort();

    }

    if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {

    if (qemu_loglevel_mask(CPU_LOG_INT)

        && cs->exception_index != EXCP_EXT_INTERRUPT) {

        qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"

                 "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",

                 __func__, env->active_tc.PC, env->CP0_EPC, cause,

target-mips/op_helper.c

+2 −1
Original line number Diff line number Diff line
@@ -38,7 +38,8 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, 
    CPUState *cs = CPU(mips_env_get_cpu(env));



    if (exception < EXCP_SC) {

        qemu_log("%s: %d %d\n", __func__, exception, error_code);

        qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",

                      __func__, exception, error_code);

    }

    cs->exception_index = exception;

    env->error_code = error_code;

target-mips/translate.c

+6 −8
Original line number Diff line number Diff line
@@ -2153,11 +2153,10 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, 
        tcg_gen_andi_tl(t0, t0, ~7);

        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);

        tcg_gen_shl_tl(t0, t0, t1);

        tcg_gen_xori_tl(t1, t1, 63);

        t2 = tcg_const_tl(0x7fffffffffffffffull);

        tcg_gen_shr_tl(t2, t2, t1);

        t2 = tcg_const_tl(-1);

        tcg_gen_shl_tl(t2, t2, t1);

        gen_load_gpr(t1, rt);

        tcg_gen_and_tl(t1, t1, t2);

        tcg_gen_andc_tl(t1, t1, t2);

        tcg_temp_free(t2);

        tcg_gen_or_tl(t0, t0, t1);

        tcg_temp_free(t1);
@@ -2246,11 +2245,10 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, 
        tcg_gen_andi_tl(t0, t0, ~3);

        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);

        tcg_gen_shl_tl(t0, t0, t1);

        tcg_gen_xori_tl(t1, t1, 31);

        t2 = tcg_const_tl(0x7fffffffull);

        tcg_gen_shr_tl(t2, t2, t1);

        t2 = tcg_const_tl(-1);

        tcg_gen_shl_tl(t2, t2, t1);

        gen_load_gpr(t1, rt);

        tcg_gen_and_tl(t1, t1, t2);

        tcg_gen_andc_tl(t1, t1, t2);

        tcg_temp_free(t2);

        tcg_gen_or_tl(t0, t0, t1);

        tcg_temp_free(t1);