Loading hw/isa/vt82c686.c +26 −14 Original line number Diff line number Diff line Loading @@ -43,10 +43,12 @@ typedef struct SuperIOConfig typedef struct VT82C686BState { PCIDevice dev; MemoryRegion superio; SuperIOConfig superio_conf; } VT82C686BState; static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data) static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data, unsigned size) { int can_write; SuperIOConfig *superio_conf = opaque; Loading Loading @@ -93,7 +95,7 @@ static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data) } } static uint32_t superio_ioport_readb(void *opaque, uint32_t addr) static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size) { SuperIOConfig *superio_conf = opaque; Loading @@ -101,6 +103,16 @@ static uint32_t superio_ioport_readb(void *opaque, uint32_t addr) return (superio_conf->config[superio_conf->index]); } static const MemoryRegionOps superio_ops = { .read = superio_ioport_readb, .write = superio_ioport_writeb, .endianness = DEVICE_NATIVE_ENDIAN, .impl = { .min_access_size = 1, .max_access_size = 1, }, }; static void vt82c686b_reset(void * opaque) { PCIDevice *d = opaque; Loading Loading @@ -140,17 +152,7 @@ static void vt82c686b_write_config(PCIDevice * d, uint32_t address, pci_default_write_config(d, address, val, len); if (address == 0x85) { /* enable or disable super IO configure */ if (val & 0x2) { /* floppy also uses 0x3f0 and 0x3f1. * But we do not emulate flopy,so just set it here. */ isa_unassign_ioport(0x3f0, 2); register_ioport_read(0x3f0, 2, 1, superio_ioport_readb, &vt686->superio_conf); register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb, &vt686->superio_conf); } else { isa_unassign_ioport(0x3f0, 2); } memory_region_set_enabled(&vt686->superio, val & 0x2); } } Loading Loading @@ -423,11 +425,13 @@ static const VMStateDescription vmstate_via = { /* init the PCI-to-ISA bridge */ static int vt82c686b_initfn(PCIDevice *d) { VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d); uint8_t *pci_conf; ISABus *isa_bus; uint8_t *wmask; int i; isa_bus_new(&d->qdev, pci_address_space_io(d)); isa_bus = isa_bus_new(&d->qdev, pci_address_space_io(d)); pci_conf = d->config; pci_config_set_prog_interface(pci_conf, 0x0); Loading @@ -439,6 +443,14 @@ static int vt82c686b_initfn(PCIDevice *d) } } memory_region_init_io(&vt82c->superio, &superio_ops, &vt82c->superio_conf, "superio", 2); memory_region_set_enabled(&vt82c->superio, false); /* The floppy also uses 0x3f0 and 0x3f1. * But we do not emulate a floppy, so just set it here. */ memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, &vt82c->superio); qemu_register_reset(vt82c686b_reset, d); return 0; Loading Loading
hw/isa/vt82c686.c +26 −14 Original line number Diff line number Diff line Loading @@ -43,10 +43,12 @@ typedef struct SuperIOConfig typedef struct VT82C686BState { PCIDevice dev; MemoryRegion superio; SuperIOConfig superio_conf; } VT82C686BState; static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data) static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data, unsigned size) { int can_write; SuperIOConfig *superio_conf = opaque; Loading Loading @@ -93,7 +95,7 @@ static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data) } } static uint32_t superio_ioport_readb(void *opaque, uint32_t addr) static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size) { SuperIOConfig *superio_conf = opaque; Loading @@ -101,6 +103,16 @@ static uint32_t superio_ioport_readb(void *opaque, uint32_t addr) return (superio_conf->config[superio_conf->index]); } static const MemoryRegionOps superio_ops = { .read = superio_ioport_readb, .write = superio_ioport_writeb, .endianness = DEVICE_NATIVE_ENDIAN, .impl = { .min_access_size = 1, .max_access_size = 1, }, }; static void vt82c686b_reset(void * opaque) { PCIDevice *d = opaque; Loading Loading @@ -140,17 +152,7 @@ static void vt82c686b_write_config(PCIDevice * d, uint32_t address, pci_default_write_config(d, address, val, len); if (address == 0x85) { /* enable or disable super IO configure */ if (val & 0x2) { /* floppy also uses 0x3f0 and 0x3f1. * But we do not emulate flopy,so just set it here. */ isa_unassign_ioport(0x3f0, 2); register_ioport_read(0x3f0, 2, 1, superio_ioport_readb, &vt686->superio_conf); register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb, &vt686->superio_conf); } else { isa_unassign_ioport(0x3f0, 2); } memory_region_set_enabled(&vt686->superio, val & 0x2); } } Loading Loading @@ -423,11 +425,13 @@ static const VMStateDescription vmstate_via = { /* init the PCI-to-ISA bridge */ static int vt82c686b_initfn(PCIDevice *d) { VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d); uint8_t *pci_conf; ISABus *isa_bus; uint8_t *wmask; int i; isa_bus_new(&d->qdev, pci_address_space_io(d)); isa_bus = isa_bus_new(&d->qdev, pci_address_space_io(d)); pci_conf = d->config; pci_config_set_prog_interface(pci_conf, 0x0); Loading @@ -439,6 +443,14 @@ static int vt82c686b_initfn(PCIDevice *d) } } memory_region_init_io(&vt82c->superio, &superio_ops, &vt82c->superio_conf, "superio", 2); memory_region_set_enabled(&vt82c->superio, false); /* The floppy also uses 0x3f0 and 0x3f1. * But we do not emulate a floppy, so just set it here. */ memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, &vt82c->superio); qemu_register_reset(vt82c686b_reset, d); return 0; Loading