Commit bc79082e authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging 



X86 queue, 2015-10-23

# gpg: Signature made Fri 23 Oct 2015 16:30:58 BST using RSA key ID 984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"

* remotes/ehabkost/tags/x86-pull-request:
  vl: trivial: minor tweaks to a max-cpu error msg
  target-i386: Use 1UL for bit shift
  target-i386: Add DE to TCG_FEATURES
  target-i386: Ensure always-1 bits on DR6 can't be cleared
  target-i386: Check CR4[DE] for processing DR4/DR5
  target-i386: Handle I/O breakpoints
  target-i386: Optimize setting dr[0-3]
  target-i386: Move hw_*breakpoint_* functions
  target-i386: Ensure bit 10 on DR7 is never cleared
  target-i386: Re-introduce optimal breakpoint removal
  target-i386: Introduce cpu_x86_update_dr7
  target-i386: Disable cache info passthrough by default
  target-i386: allow any alignment for SMBASE

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 1e700f4c 31bfa2a4

include/hw/i386/pc.h

+5 −0
Original line number Diff line number Diff line
@@ -318,6 +318,11 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); 
            .driver   = "Broadwell-noTSX-" TYPE_X86_CPU,\

            .property = "abm",\

            .value    = "off",\

        },\

        {\

            .driver   = "host" "-" TYPE_X86_CPU,\

            .property = "host-cache-info",\

            .value    = "on",\

        },



#define PC_COMPAT_2_3 \

target-i386/bpt_helper.c

+184 −40
Original line number Diff line number Diff line
@@ -21,64 +21,147 @@ 
#include "exec/helper-proto.h"





void hw_breakpoint_insert(CPUX86State *env, int index)

#ifndef CONFIG_USER_ONLY

static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)

{

    return (dr7 >> (index * 2)) & 1;

}



static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index)

{

    return (dr7 >> (index * 2)) & 2;



}

static inline bool hw_breakpoint_enabled(unsigned long dr7, int index)

{

    return hw_global_breakpoint_enabled(dr7, index) ||

           hw_local_breakpoint_enabled(dr7, index);

}



static inline int hw_breakpoint_type(unsigned long dr7, int index)

{

    return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;

}



static inline int hw_breakpoint_len(unsigned long dr7, int index)

{

    int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);

    return (len == 2) ? 8 : len + 1;

}



static int hw_breakpoint_insert(CPUX86State *env, int index)

{

    CPUState *cs = CPU(x86_env_get_cpu(env));

    int type = 0, err = 0;

    target_ulong dr7 = env->dr[7];

    target_ulong drN = env->dr[index];

    int err = 0;



    switch (hw_breakpoint_type(env->dr[7], index)) {

    switch (hw_breakpoint_type(dr7, index)) {

    case DR7_TYPE_BP_INST:

        if (hw_breakpoint_enabled(env->dr[7], index)) {

            err = cpu_breakpoint_insert(cs, env->dr[index], BP_CPU,

        if (hw_breakpoint_enabled(dr7, index)) {

            err = cpu_breakpoint_insert(cs, drN, BP_CPU,

                                        &env->cpu_breakpoint[index]);

        }

        break;

    case DR7_TYPE_DATA_WR:

        type = BP_CPU | BP_MEM_WRITE;

        break;



    case DR7_TYPE_IO_RW:

        /* No support for I/O watchpoints yet */

        /* Notice when we should enable calls to bpt_io.  */

        return hw_breakpoint_enabled(env->dr[7], index)

               ? HF_IOBPT_MASK : 0;



    case DR7_TYPE_DATA_WR:

        if (hw_breakpoint_enabled(dr7, index)) {

            err = cpu_watchpoint_insert(cs, drN,

                                        hw_breakpoint_len(dr7, index),

                                        BP_CPU | BP_MEM_WRITE,

                                        &env->cpu_watchpoint[index]);

        }

        break;



    case DR7_TYPE_DATA_RW:

        type = BP_CPU | BP_MEM_ACCESS;

        break;

        if (hw_breakpoint_enabled(dr7, index)) {

            err = cpu_watchpoint_insert(cs, drN,

                                        hw_breakpoint_len(dr7, index),

                                        BP_CPU | BP_MEM_ACCESS,

                                        &env->cpu_watchpoint[index]);

        }



    if (type != 0) {

        err = cpu_watchpoint_insert(cs, env->dr[index],

                                    hw_breakpoint_len(env->dr[7], index),

                                    type, &env->cpu_watchpoint[index]);

        break;

    }



    if (err) {

        env->cpu_breakpoint[index] = NULL;

    }

    return 0;

}



void hw_breakpoint_remove(CPUX86State *env, int index)

static void hw_breakpoint_remove(CPUX86State *env, int index)

{

    CPUState *cs;

    CPUState *cs = CPU(x86_env_get_cpu(env));



    if (!env->cpu_breakpoint[index]) {

        return;

    }

    cs = CPU(x86_env_get_cpu(env));

    switch (hw_breakpoint_type(env->dr[7], index)) {

    case DR7_TYPE_BP_INST:

        if (hw_breakpoint_enabled(env->dr[7], index)) {

        if (env->cpu_breakpoint[index]) {

            cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]);

            env->cpu_breakpoint[index] = NULL;

        }

        break;



    case DR7_TYPE_DATA_WR:

    case DR7_TYPE_DATA_RW:

        if (env->cpu_breakpoint[index]) {

            cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]);

            env->cpu_breakpoint[index] = NULL;

        }

        break;



    case DR7_TYPE_IO_RW:

        /* No support for I/O watchpoints yet */

        /* HF_IOBPT_MASK cleared elsewhere.  */

        break;

    }

}



void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7)

{

    target_ulong old_dr7 = env->dr[7];

    int iobpt = 0;

    int i;



    new_dr7 |= DR7_FIXED_1;



    /* If nothing is changing except the global/local enable bits,

       then we can make the change more efficient.  */

    if (((old_dr7 ^ new_dr7) & ~0xff) == 0) {

        /* Fold the global and local enable bits together into the

           global fields, then xor to show which registers have

           changed collective enable state.  */

        int mod = ((old_dr7 | old_dr7 * 2) ^ (new_dr7 | new_dr7 * 2)) & 0xff;



        for (i = 0; i < DR7_MAX_BP; i++) {

            if ((mod & (2 << i * 2)) && !hw_breakpoint_enabled(new_dr7, i)) {

                hw_breakpoint_remove(env, i);

            }

        }

        env->dr[7] = new_dr7;

        for (i = 0; i < DR7_MAX_BP; i++) {

            if (mod & (2 << i * 2) && hw_breakpoint_enabled(new_dr7, i)) {

                iobpt |= hw_breakpoint_insert(env, i);

            } else if (hw_breakpoint_type(new_dr7, i) == DR7_TYPE_IO_RW

                       && hw_breakpoint_enabled(new_dr7, i)) {

                iobpt |= HF_IOBPT_MASK;

            }

        }

    } else {

        for (i = 0; i < DR7_MAX_BP; i++) {

            hw_breakpoint_remove(env, i);

        }

        env->dr[7] = new_dr7;

        for (i = 0; i < DR7_MAX_BP; i++) {

            iobpt |= hw_breakpoint_insert(env, i);

        }

    }



    env->hflags = (env->hflags & ~HF_IOBPT_MASK) | iobpt;

}



static bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update)

{

    target_ulong dr6;
@@ -148,6 +231,7 @@ void breakpoint_handler(CPUState *cs) 
        }

    }

}

#endif



void helper_single_step(CPUX86State *env)

{
@@ -158,25 +242,85 @@ void helper_single_step(CPUX86State *env) 
    raise_exception(env, EXCP01_DB);

}



void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)

void helper_set_dr(CPUX86State *env, int reg, target_ulong t0)

{

#ifndef CONFIG_USER_ONLY

    int i;



    if (reg < 4) {

    switch (reg) {

    case 0: case 1: case 2: case 3:

        if (hw_breakpoint_enabled(env->dr[7], reg)

            && hw_breakpoint_type(env->dr[7], reg) != DR7_TYPE_IO_RW) {

            hw_breakpoint_remove(env, reg);

            env->dr[reg] = t0;

            hw_breakpoint_insert(env, reg);

    } else if (reg == 7) {

        for (i = 0; i < DR7_MAX_BP; i++) {

            hw_breakpoint_remove(env, i);

        } else {

            env->dr[reg] = t0;

        }

        env->dr[7] = t0;

        for (i = 0; i < DR7_MAX_BP; i++) {

            hw_breakpoint_insert(env, i);

        return;

    case 4:

        if (env->cr[4] & CR4_DE_MASK) {

            break;

        }

        /* fallthru */

    case 6:

        env->dr[6] = t0 | DR6_FIXED_1;

        return;

    case 5:

        if (env->cr[4] & CR4_DE_MASK) {

            break;

        }

        /* fallthru */

    case 7:

        cpu_x86_update_dr7(env, t0);

        return;

    }

    raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());

#endif

}



target_ulong helper_get_dr(CPUX86State *env, int reg)

{

    switch (reg) {

    case 0: case 1: case 2: case 3: case 6: case 7:

        return env->dr[reg];

    case 4:

        if (env->cr[4] & CR4_DE_MASK) {

            break;

        } else {

        env->dr[reg] = t0;

            return env->dr[6];

        }

    case 5:

        if (env->cr[4] & CR4_DE_MASK) {

            break;

        } else {

            return env->dr[7];

        }

    }

    raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());

}



/* Check if Port I/O is trapped by a breakpoint.  */

void helper_bpt_io(CPUX86State *env, uint32_t port,

                   uint32_t size, target_ulong next_eip)

{

#ifndef CONFIG_USER_ONLY

    target_ulong dr7 = env->dr[7];

    int i, hit = 0;



    for (i = 0; i < DR7_MAX_BP; ++i) {

        if (hw_breakpoint_type(dr7, i) == DR7_TYPE_IO_RW

            && hw_breakpoint_enabled(dr7, i)) {

            int bpt_len = hw_breakpoint_len(dr7, i);

            if (port + size - 1 >= env->dr[i]

                && port <= env->dr[i] + bpt_len - 1) {

                hit |= 1 << i;

            }

        }

    }



    if (hit) {

        env->dr[6] = (env->dr[6] & ~0xf) | hit;

        env->eip = next_eip;

        raise_exception(env, EXCP01_DB);

    }

#endif

}

target-i386/cpu.c

+3 −5
Original line number Diff line number Diff line
@@ -312,7 +312,7 @@ static const char *cpuid_6_feature_name[] = { 
          CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \

          CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \

          CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \

          CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)

          CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)

          /* partly implemented:

          CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */

          /* missing:
@@ -656,7 +656,6 @@ struct X86CPUDefinition { 
    int stepping;

    FeatureWordArray features;

    char model_id[48];

    bool cache_info_passthrough;

};



static X86CPUDefinition builtin_x86_defs[] = {
@@ -1420,6 +1419,7 @@ static X86CPUDefinition host_cpudef; 


static Property host_x86_cpu_properties[] = {

    DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),

    DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),

    DEFINE_PROP_END_OF_LIST()

};
@@ -1446,7 +1446,6 @@ static void host_x86_cpu_class_init(ObjectClass *oc, void *data) 
    cpu_x86_fill_model_id(host_cpudef.model_id);



    xcc->cpu_def = &host_cpudef;

    host_cpudef.cache_info_passthrough = true;



    /* level, xlevel, xlevel2, and the feature words are initialized on

     * instance_init, because they require KVM to be initialized.
@@ -1492,7 +1491,7 @@ static void report_unavailable_features(FeatureWord w, uint32_t mask) 
    int i;



    for (i = 0; i < 32; ++i) {

        if (1 << i & mask) {

        if ((1UL << i) & mask) {

            const char *reg = get_register_name_32(f->cpuid_reg);

            assert(reg);

            fprintf(stderr, "warning: %s doesn't support requested feature: "
@@ -2094,7 +2093,6 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp) 
    object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);

    object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);

    object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);

    cpu->cache_info_passthrough = def->cache_info_passthrough;

    object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);

    for (w = 0; w < FEATURE_WORDS; w++) {

        env->features[w] = def->features[w];

target-i386/cpu.h

+5 −30
Original line number Diff line number Diff line
@@ -155,6 +155,7 @@ 
#define HF_SVMI_SHIFT       21 /* SVM intercepts are active */

#define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */

#define HF_SMAP_SHIFT       23 /* CR4.SMAP */

#define HF_IOBPT_SHIFT      24 /* an io breakpoint enabled */



#define HF_CPL_MASK          (3 << HF_CPL_SHIFT)

#define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
@@ -178,6 +179,7 @@ 
#define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)

#define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)

#define HF_SMAP_MASK         (1 << HF_SMAP_SHIFT)

#define HF_IOBPT_MASK        (1 << HF_IOBPT_SHIFT)



/* hflags2 */
@@ -235,6 +237,7 @@ 
#define DR7_TYPE_SHIFT  16

#define DR7_LEN_SHIFT   18

#define DR7_FIXED_1     0x00000400

#define DR7_GLOBAL_BP_MASK   0xaa

#define DR7_LOCAL_BP_MASK    0x55

#define DR7_MAX_BP           4

#define DR7_TYPE_BP_INST     0x0
@@ -917,7 +920,7 @@ typedef struct CPUX86State { 
    int error_code;

    int exception_is_int;

    target_ulong exception_next_eip;

    target_ulong dr[8]; /* debug registers */

    target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */

    union {

        struct CPUBreakpoint *cpu_breakpoint[4];

        struct CPUWatchpoint *cpu_watchpoint[4];
@@ -1127,41 +1130,13 @@ void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); 
void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);

#endif



static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)

{

    return (dr7 >> (index * 2)) & 1;

}



static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index)

{

    return (dr7 >> (index * 2)) & 2;



}

static inline bool hw_breakpoint_enabled(unsigned long dr7, int index)

{

    return hw_global_breakpoint_enabled(dr7, index) ||

           hw_local_breakpoint_enabled(dr7, index);

}



static inline int hw_breakpoint_type(unsigned long dr7, int index)

{

    return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;

}



static inline int hw_breakpoint_len(unsigned long dr7, int index)

{

    int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);

    return (len == 2) ? 8 : len + 1;

}



void hw_breakpoint_insert(CPUX86State *env, int index);

void hw_breakpoint_remove(CPUX86State *env, int index);

void breakpoint_handler(CPUState *cs);



/* will be suppressed */

void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);

void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);

void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);

void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);



/* hw/pc.c */

uint64_t cpu_get_tsc(CPUX86State *env);

target-i386/helper.h

+3 −1
Original line number Diff line number Diff line
@@ -40,7 +40,8 @@ DEF_HELPER_2(read_crN, tl, env, int) 
DEF_HELPER_3(write_crN, void, env, int, tl)

DEF_HELPER_2(lmsw, void, env, tl)

DEF_HELPER_1(clts, void, env)

DEF_HELPER_3(movl_drN_T0, void, env, int, tl)

DEF_HELPER_FLAGS_3(set_dr, TCG_CALL_NO_WG, void, env, int, tl)

DEF_HELPER_FLAGS_2(get_dr, TCG_CALL_NO_WG, tl, env, int)

DEF_HELPER_2(invlpg, void, env, tl)



DEF_HELPER_4(enter_level, void, env, int, int, tl)
@@ -92,6 +93,7 @@ DEF_HELPER_3(outw, void, env, i32, i32) 
DEF_HELPER_2(inw, tl, env, i32)

DEF_HELPER_3(outl, void, env, i32, i32)

DEF_HELPER_2(inl, tl, env, i32)

DEF_HELPER_FLAGS_4(bpt_io, TCG_CALL_NO_WG, void, env, i32, i32, tl)



DEF_HELPER_3(svm_check_intercept_param, void, env, i32, i64)

DEF_HELPER_3(vmexit, void, env, i32, i64)