Commit bbca1067 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190121' into staging 



target-arm queue:
 * hw/char/stm32f2xx_usart: Do not update data register when device is disabled
 * hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node
 * target/arm: Allow Aarch32 exception return to switch from Mon->Hyp
 * ftgmac100: implement the new MDIO interface on Aspeed SoC
 * implement the ARMv8.3-PAuth extension
 * improve emulation of the ARM PMU

# gpg: Signature made Mon 21 Jan 2019 10:42:11 GMT
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190121: (48 commits)
  target/arm: Implement PMSWINC
  target/arm: PMU: Set PMCR.N to 4
  target/arm: PMU: Add instruction and cycle events
  target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
  target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0
  target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
  target/arm: Define FIELDs for ID_DFR0
  target/arm: Implement PMOVSSET
  target/arm: Allow AArch32 access for PMCCFILTR
  target/arm: Filter cycle counter based on PMCCFILTR_EL0
  target/arm: Swap PMU values before/after migrations
  target/arm: Reorganize PMCCNTR accesses
  migration: Add post_save function to VMStateDescription
  target/arm: Tidy TBI handling in gen_a64_set_pc
  target/arm: Enable PAuth for user-only
  target/arm: Enable PAuth for -cpu max
  target/arm: Add PAuth system registers
  target/arm: Implement pauth_computepac
  target/arm: Implement pauth_addpac
  target/arm: Implement pauth_auth
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents f1231399 0d4bfd7d

docs/devel/migration.rst

+7 −2
Original line number Diff line number Diff line
@@ -419,8 +419,13 @@ The functions to do that are inside a vmstate definition, and are called: 


  This function is called before we save the state of one device.



Example: You can look at hpet.c, that uses the three function to

massage the state that is transferred.

- ``int (*post_save)(void *opaque);``



  This function is called after we save the state of one device

  (even upon failure, unless the call to pre_save returned an error).



Example: You can look at hpet.c, that uses the first three functions

to massage the state that is transferred.



The ``VMSTATE_WITH_TMP`` macro may be useful when the migration

data doesn't match the stored device data well; it allows an

hw/arm/virt-acpi-build.c

+1 −0
Original line number Diff line number Diff line
@@ -418,6 +418,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) 
        smmu->mapping_count = cpu_to_le32(1);

        smmu->mapping_offset = cpu_to_le32(sizeof(*smmu));

        smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base);

        smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);

        smmu->event_gsiv = cpu_to_le32(irq);

        smmu->pri_gsiv = cpu_to_le32(irq + 1);

        smmu->gerr_gsiv = cpu_to_le32(irq + 2);

hw/char/stm32f2xx_usart.c

+1 −2
Original line number Diff line number Diff line
@@ -53,14 +53,13 @@ static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size) 
{

    STM32F2XXUsartState *s = opaque;



    s->usart_dr = *buf;



    if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {

        /* USART not enabled - drop the chars */

        DB_PRINT("Dropping the chars\n");

        return;

    }



    s->usart_dr = *buf;

    s->usart_sr |= USART_SR_RXNE;



    if (s->usart_cr1 & USART_CR1_RXNEIE) {

hw/net/ftgmac100.c

+68 −12
Original line number Diff line number Diff line
@@ -89,6 +89,18 @@ 
#define FTGMAC100_PHYDATA_MIIWDATA(x)       ((x) & 0xffff)

#define FTGMAC100_PHYDATA_MIIRDATA(x)       (((x) >> 16) & 0xffff)



/*

 * PHY control register - New MDC/MDIO interface

 */

#define FTGMAC100_PHYCR_NEW_DATA(x)     (((x) >> 16) & 0xffff)

#define FTGMAC100_PHYCR_NEW_FIRE        (1 << 15)

#define FTGMAC100_PHYCR_NEW_ST_22       (1 << 12)

#define FTGMAC100_PHYCR_NEW_OP(x)       (((x) >> 10) & 3)

#define   FTGMAC100_PHYCR_NEW_OP_WRITE    0x1

#define   FTGMAC100_PHYCR_NEW_OP_READ     0x2

#define FTGMAC100_PHYCR_NEW_DEV(x)      (((x) >> 5) & 0x1f)

#define FTGMAC100_PHYCR_NEW_REG(x)      ((x) & 0x1f)



/*

 * Feature Register

 */
@@ -269,9 +281,9 @@ static void phy_reset(FTGMAC100State *s) 
    s->phy_int = 0;

}



static uint32_t do_phy_read(FTGMAC100State *s, int reg)

static uint16_t do_phy_read(FTGMAC100State *s, uint8_t reg)

{

    uint32_t val;

    uint16_t val;



    switch (reg) {

    case MII_BMCR: /* Basic Control */
@@ -336,7 +348,7 @@ static uint32_t do_phy_read(FTGMAC100State *s, int reg) 
                       MII_BMCR_FD | MII_BMCR_CTST)

#define MII_ANAR_MASK 0x2d7f



static void do_phy_write(FTGMAC100State *s, int reg, uint32_t val)

static void do_phy_write(FTGMAC100State *s, uint8_t reg, uint16_t val)

{

    switch (reg) {

    case MII_BMCR:     /* Basic Control */
@@ -373,6 +385,55 @@ static void do_phy_write(FTGMAC100State *s, int reg, uint32_t val) 
    }

}



static void do_phy_new_ctl(FTGMAC100State *s)

{

    uint8_t reg;

    uint16_t data;



    if (!(s->phycr & FTGMAC100_PHYCR_NEW_ST_22)) {

        qemu_log_mask(LOG_UNIMP, "%s: unsupported ST code\n", __func__);

        return;

    }



    /* Nothing to do */

    if (!(s->phycr & FTGMAC100_PHYCR_NEW_FIRE)) {

        return;

    }



    reg = FTGMAC100_PHYCR_NEW_REG(s->phycr);

    data = FTGMAC100_PHYCR_NEW_DATA(s->phycr);



    switch (FTGMAC100_PHYCR_NEW_OP(s->phycr)) {

    case FTGMAC100_PHYCR_NEW_OP_WRITE:

        do_phy_write(s, reg, data);

        break;

    case FTGMAC100_PHYCR_NEW_OP_READ:

        s->phydata = do_phy_read(s, reg) & 0xffff;

        break;

    default:

        qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid OP code %08x\n",

                      __func__, s->phycr);

    }



    s->phycr &= ~FTGMAC100_PHYCR_NEW_FIRE;

}



static void do_phy_ctl(FTGMAC100State *s)

{

    uint8_t reg = FTGMAC100_PHYCR_REG(s->phycr);



    if (s->phycr & FTGMAC100_PHYCR_MIIWR) {

        do_phy_write(s, reg, s->phydata & 0xffff);

        s->phycr &= ~FTGMAC100_PHYCR_MIIWR;

    } else if (s->phycr & FTGMAC100_PHYCR_MIIRD) {

        s->phydata = do_phy_read(s, reg) << 16;

        s->phycr &= ~FTGMAC100_PHYCR_MIIRD;

    } else {

        qemu_log_mask(LOG_GUEST_ERROR, "%s: no OP code %08x\n",

                      __func__, s->phycr);

    }

}



static int ftgmac100_read_bd(FTGMAC100Desc *bd, dma_addr_t addr)

{

    if (dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd))) {
@@ -628,7 +689,6 @@ static void ftgmac100_write(void *opaque, hwaddr addr, 
                          uint64_t value, unsigned size)

{

    FTGMAC100State *s = FTGMAC100(opaque);

    int reg;



    switch (addr & 0xff) {

    case FTGMAC100_ISR: /* Interrupt status */
@@ -711,14 +771,11 @@ static void ftgmac100_write(void *opaque, hwaddr addr, 
        break;



    case FTGMAC100_PHYCR:  /* PHY Device control */

        reg = FTGMAC100_PHYCR_REG(value);

        s->phycr = value;

        if (value & FTGMAC100_PHYCR_MIIWR) {

            do_phy_write(s, reg, s->phydata & 0xffff);

            s->phycr &= ~FTGMAC100_PHYCR_MIIWR;

        if (s->revr & FTGMAC100_REVR_NEW_MDIO_INTERFACE) {

            do_phy_new_ctl(s);

        } else {

            s->phydata = do_phy_read(s, reg) << 16;

            s->phycr &= ~FTGMAC100_PHYCR_MIIRD;

            do_phy_ctl(s);

        }

        break;

    case FTGMAC100_PHYDATA:
@@ -728,8 +785,7 @@ static void ftgmac100_write(void *opaque, hwaddr addr, 
        s->dblac = value;

        break;

    case FTGMAC100_REVR:  /* Feature Register */

        /* TODO: Only Old MDIO interface is supported */

        s->revr = value & ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;

        s->revr = value;

        break;

    case FTGMAC100_FEAR1: /* Feature Register 1 */

        s->fear1 = value;

include/hw/acpi/acpi-defs.h

+2 −0
Original line number Diff line number Diff line
@@ -626,6 +626,8 @@ struct AcpiIortItsGroup { 
} QEMU_PACKED;

typedef struct AcpiIortItsGroup AcpiIortItsGroup;



#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE 1



struct AcpiIortSmmu3 {

    ACPI_IORT_NODE_HEADER_DEF

    uint64_t base_address;