Loading cputlb.c +1 −1 Original line number Diff line number Diff line Loading @@ -119,7 +119,7 @@ void tlb_protect_code(ram_addr_t ram_addr) /* update the TLB so that writes in physical page 'phys_addr' are no longer tested for self modifying code */ void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr, void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr, target_ulong vaddr) { cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_CODE); Loading include/exec/cputlb.h +1 −1 Original line number Diff line number Diff line Loading @@ -22,7 +22,7 @@ #if !defined(CONFIG_USER_ONLY) /* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr, void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr, target_ulong vaddr); void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start, uintptr_t length); Loading translate-all.c +3 −3 Original line number Diff line number Diff line Loading @@ -1007,7 +1007,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, { TranslationBlock *tb, *tb_next, *saved_tb; CPUState *cpu = current_cpu; #if defined(TARGET_HAS_PRECISE_SMC) || !defined(CONFIG_USER_ONLY) #if defined(TARGET_HAS_PRECISE_SMC) CPUArchState *env = NULL; #endif tb_page_addr_t tb_start, tb_end; Loading @@ -1032,7 +1032,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, /* build code bitmap */ build_page_bitmap(p); } #if defined(TARGET_HAS_PRECISE_SMC) || !defined(CONFIG_USER_ONLY) #if defined(TARGET_HAS_PRECISE_SMC) if (cpu != NULL) { env = cpu->env_ptr; } Loading Loading @@ -1102,7 +1102,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, if (!p->first_tb) { invalidate_page_bitmap(p); if (is_cpu_write_access) { tlb_unprotect_code_phys(env, start, cpu->mem_io_vaddr); tlb_unprotect_code_phys(cpu, start, cpu->mem_io_vaddr); } } #endif Loading Loading
cputlb.c +1 −1 Original line number Diff line number Diff line Loading @@ -119,7 +119,7 @@ void tlb_protect_code(ram_addr_t ram_addr) /* update the TLB so that writes in physical page 'phys_addr' are no longer tested for self modifying code */ void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr, void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr, target_ulong vaddr) { cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_CODE); Loading
include/exec/cputlb.h +1 −1 Original line number Diff line number Diff line Loading @@ -22,7 +22,7 @@ #if !defined(CONFIG_USER_ONLY) /* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr, void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr, target_ulong vaddr); void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start, uintptr_t length); Loading
translate-all.c +3 −3 Original line number Diff line number Diff line Loading @@ -1007,7 +1007,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, { TranslationBlock *tb, *tb_next, *saved_tb; CPUState *cpu = current_cpu; #if defined(TARGET_HAS_PRECISE_SMC) || !defined(CONFIG_USER_ONLY) #if defined(TARGET_HAS_PRECISE_SMC) CPUArchState *env = NULL; #endif tb_page_addr_t tb_start, tb_end; Loading @@ -1032,7 +1032,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, /* build code bitmap */ build_page_bitmap(p); } #if defined(TARGET_HAS_PRECISE_SMC) || !defined(CONFIG_USER_ONLY) #if defined(TARGET_HAS_PRECISE_SMC) if (cpu != NULL) { env = cpu->env_ptr; } Loading Loading @@ -1102,7 +1102,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, if (!p->first_tb) { invalidate_page_bitmap(p); if (is_cpu_write_access) { tlb_unprotect_code_phys(env, start, cpu->mem_io_vaddr); tlb_unprotect_code_phys(cpu, start, cpu->mem_io_vaddr); } } #endif Loading