Commit ba2ed84f authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf1' into staging 



RISC-V Patches for the 5.0 Soft Freeze, Part 1

This patch set contains a handful of collected fixes that I'd like to target
for the 5.0 soft freeze (I know that's a long way away, I just don't know what
else to call these):

* A fix for a memory leak initializing the sifive_u board.
* Fixes to privilege mode emulation related to interrupts and fstatus.

Notably absent is the H extension implementation.  That's pretty much reviewed,
but not quite ready to go yet and I didn't want to hold back these important
fixes.  This boots 32-bit and 64-bit Linux (buildroot this time, just for fun)
and passes "make check".

# gpg: Signature made Tue 21 Jan 2020 22:55:28 GMT
# gpg:                using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889
# gpg:                issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41
#      Subkey fingerprint: 2B3C 3747 4468 43B2 4A94  3A7A 2E13 19F3 5FBB 1889

* remotes/palmer/tags/riscv-for-master-5.0-sf1:
  target/riscv: update mstatus.SD when FS is set dirty
  target/riscv: fsd/fsw doesn't dirty FP state
  target/riscv: Fix tb->flags FS status
  riscv: Set xPIE to 1 after xRET
  riscv/sifive_u: fix a memory leak in soc_realize()

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents a43efa34 82f01467

hw/riscv/sifive_u.c

+1 −0
Original line number Diff line number Diff line
@@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) 
        SIFIVE_U_PLIC_CONTEXT_BASE,

        SIFIVE_U_PLIC_CONTEXT_STRIDE,

        memmap[SIFIVE_U_PLIC].size);

    g_free(plic_hart_config);

    sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,

        serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));

    sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,

target/riscv/cpu.h

+1 −4
Original line number Diff line number Diff line
@@ -293,10 +293,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 
#ifdef CONFIG_USER_ONLY

    *flags = TB_FLAGS_MSTATUS_FS;

#else

    *flags = cpu_mmu_index(env, 0);

    if (riscv_cpu_fp_enabled(env)) {

        *flags |= TB_FLAGS_MSTATUS_FS;

    }

    *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);

#endif

}

target/riscv/csr.c

+1 −2
Original line number Diff line number Diff line
@@ -341,8 +341,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) 


    mstatus = (mstatus & ~mask) | (val & mask);



    dirty = (riscv_cpu_fp_enabled(env) &&

             ((mstatus & MSTATUS_FS) == MSTATUS_FS)) |

    dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |

            ((mstatus & MSTATUS_XS) == MSTATUS_XS);

    mstatus = set_field(mstatus, MSTATUS_SD, dirty);

    env->mstatus = mstatus;

target/riscv/insn_trans/trans_rvd.inc.c

+0 −1
Original line number Diff line number Diff line
@@ -43,7 +43,6 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) 


    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);



    mark_fs_dirty(ctx);

    tcg_temp_free(t0);

    return true;

}

target/riscv/insn_trans/trans_rvf.inc.c

+0 −1
Original line number Diff line number Diff line
@@ -52,7 +52,6 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) 
    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);



    tcg_temp_free(t0);

    mark_fs_dirty(ctx);

    return true;

}