Commit ba080b86 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Remove sve_memopidx 



None of the sve helpers use TCGMemOpIdx any longer, so we can
stop passing it.

Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20200508154359.7494-20-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 10a85e2c

target/arm/internals.h

+0 −5
Original line number Diff line number Diff line
@@ -979,11 +979,6 @@ static inline int arm_num_ctx_cmps(ARMCPU *cpu) 
    }

}



/* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3.

 * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits.

 */

#define MEMOPIDX_SHIFT  8



/**

 * v7m_using_psp: Return true if using process stack pointer

 * Return true if the CPU is currently using the process stack

target/arm/sve_helper.c

+7 −7
Original line number Diff line number Diff line
@@ -4440,7 +4440,7 @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr, 
               sve_ldst1_host_fn *host_fn,

               sve_ldst1_tlb_fn *tlb_fn)

{

    const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);

    const unsigned rd = simd_data(desc);

    const intptr_t reg_max = simd_oprsz(desc);

    intptr_t reg_off, reg_last, mem_off;

    SVEContLdSt info;
@@ -4696,7 +4696,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr, 
                   sve_ldst1_host_fn *host_fn,

                   sve_ldst1_tlb_fn *tlb_fn)

{

    const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);

    const unsigned rd = simd_data(desc);

    void *vd = &env->vfp.zregs[rd];

    const intptr_t reg_max = simd_oprsz(desc);

    intptr_t reg_off, mem_off, reg_last;
@@ -4925,7 +4925,7 @@ void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, uint32_t desc, 
               sve_ldst1_host_fn *host_fn,

               sve_ldst1_tlb_fn *tlb_fn)

{

    const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);

    const unsigned rd = simd_data(desc);

    const intptr_t reg_max = simd_oprsz(desc);

    intptr_t reg_off, reg_last, mem_off;

    SVEContLdSt info;
@@ -5131,9 +5131,9 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, 
               sve_ldst1_host_fn *host_fn,

               sve_ldst1_tlb_fn *tlb_fn)

{

    const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);

    const int mmu_idx = cpu_mmu_index(env, false);

    const intptr_t reg_max = simd_oprsz(desc);

    const int scale = simd_data(desc);

    ARMVectorReg scratch;

    intptr_t reg_off;

    SVEHostPage info, info2;
@@ -5276,10 +5276,10 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, 
                 sve_ldst1_tlb_fn *tlb_fn)

{

    const int mmu_idx = cpu_mmu_index(env, false);

    const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);

    const intptr_t reg_max = simd_oprsz(desc);

    const int scale = simd_data(desc);

    const int esize = 1 << esz;

    const int msize = 1 << msz;

    const intptr_t reg_max = simd_oprsz(desc);

    intptr_t reg_off;

    SVEHostPage info;

    target_ulong addr, in_page;
@@ -5430,9 +5430,9 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, 
               sve_ldst1_host_fn *host_fn,

               sve_ldst1_tlb_fn *tlb_fn)

{

    const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);

    const int mmu_idx = cpu_mmu_index(env, false);

    const intptr_t reg_max = simd_oprsz(desc);

    const int scale = simd_data(desc);

    void *host[ARM_MAX_VQ * 4];

    intptr_t reg_off, i;

    SVEHostPage info, info2;

target/arm/translate-sve.c

+3 −14
Original line number Diff line number Diff line
@@ -4582,11 +4582,6 @@ static const uint8_t dtype_esz[16] = { 
    3, 2, 1, 3

};



static TCGMemOpIdx sve_memopidx(DisasContext *s, int dtype)

{

    return make_memop_idx(s->be_data | dtype_mop[dtype], get_mem_index(s));

}



static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,

                       int dtype, gen_helper_gvec_mem *fn)

{
@@ -4599,9 +4594,7 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, 
     * registers as pointers, so encode the regno into the data field.

     * For consistency, do this even for LD1.

     */

    desc = sve_memopidx(s, dtype);

    desc |= zt << MEMOPIDX_SHIFT;

    desc = simd_desc(vsz, vsz, desc);

    desc = simd_desc(vsz, vsz, zt);

    t_desc = tcg_const_i32(desc);

    t_pg = tcg_temp_new_ptr();
@@ -4833,9 +4826,7 @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int msz) 
    int desc, poff;



    /* Load the first quadword using the normal predicated load helpers.  */

    desc = sve_memopidx(s, msz_dtype(s, msz));

    desc |= zt << MEMOPIDX_SHIFT;

    desc = simd_desc(16, 16, desc);

    desc = simd_desc(16, 16, zt);

    t_desc = tcg_const_i32(desc);



    poff = pred_full_reg_offset(s, pg);
@@ -5064,9 +5055,7 @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, 
    TCGv_i32 t_desc;

    int desc;



    desc = sve_memopidx(s, msz_dtype(s, msz));

    desc |= scale << MEMOPIDX_SHIFT;

    desc = simd_desc(vsz, vsz, desc);

    desc = simd_desc(vsz, vsz, scale);

    t_desc = tcg_const_i32(desc);



    tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));