Commit b98a6620 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-rc0-2' into staging 



RISC-V Patches for 4.0-rc0, Part 2

This patch set contains three major sources of bug fixes:

* Jim has added support for GDB XML files, as well as fixing access to
  CSRs via the GDB stub.
* Alistair has rebased a large set of fixes from Michael that were still
  in his patch queue.  These fix bugs all over our tree, including:
    * Logging of PMP errors.
    * User ABI cleanups and fixes, most notably on RVE guests.
    * Fixes for interrupt emulation fidelity.
    * Improvements to the emulation fidelity of the sifive_u machine.
* Bin Meng has improved the emulation fidelity of the SiFive UART, which
  now supports both TX and RX interrupts (as well as setting the correct
  interrupt line).

# gpg: Signature made Tue 19 Mar 2019 12:42:11 GMT
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.0-rc0-2:
  riscv: sifive_u: Correct UART0's IRQ in the device tree
  riscv: sifive_uart: Generate TX interrupt
  target/riscv: Remove unused struct
  riscv: sifive_u: Allow up to 4 CPUs to be created
  RISC-V: Update load reservation comment in do_interrupt
  RISC-V: Convert trap debugging to trace events
  RISC-V: Add support for vectored interrupts
  RISC-V: Change local interrupts from edge to level
  RISC-V: linux-user support for RVE ABI
  elf: Add RISC-V PSABI ELF header defines
  RISC-V: Remove unnecessary disassembler constraints
  RISC-V: Allow interrupt controllers to claim interrupts
  RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
  riscv: pmp: Log pmp access errors as guest errors
  RISC-V: Add hooks to use the gdb xml files.
  RISC-V: Add debug support for accessing CSRs.
  RISC-V: Fixes to CSR_* register macros.
  RISC-V: Add 64-bit gdb xml files.
  RISC-V: Add 32-bit gdb xml files.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 86e2fca2 a9ec1c76

Makefile.objs

+1 −0
Original line number Diff line number Diff line
@@ -186,6 +186,7 @@ trace-events-subdirs += target/hppa 
trace-events-subdirs += target/i386

trace-events-subdirs += target/mips

trace-events-subdirs += target/ppc

trace-events-subdirs += target/riscv

trace-events-subdirs += target/s390x

trace-events-subdirs += target/sparc

trace-events-subdirs += ui

configure

+2 −0
Original line number Diff line number Diff line
@@ -7514,12 +7514,14 @@ case "$target_name" in 
    TARGET_BASE_ARCH=riscv

    TARGET_ABI_DIR=riscv

    mttcg=yes

    gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml"

    target_compiler=$cross_cc_riscv32

  ;;

  riscv64)

    TARGET_BASE_ARCH=riscv

    TARGET_ABI_DIR=riscv

    mttcg=yes

    gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml"

    target_compiler=$cross_cc_riscv64

  ;;

  sh4|sh4eb)

disas/riscv.c

+0 −138
Original line number Diff line number Diff line
@@ -87,33 +87,10 @@ typedef enum { 


typedef enum {

    rvc_end,

    rvc_simm_6,

    rvc_imm_6,

    rvc_imm_7,

    rvc_imm_8,

    rvc_imm_9,

    rvc_imm_10,

    rvc_imm_12,

    rvc_imm_18,

    rvc_imm_nz,

    rvc_imm_x2,

    rvc_imm_x4,

    rvc_imm_x8,

    rvc_imm_x16,

    rvc_rd_b3,

    rvc_rs1_b3,

    rvc_rs2_b3,

    rvc_rd_eq_rs1,

    rvc_rd_eq_ra,

    rvc_rd_eq_sp,

    rvc_rd_eq_x0,

    rvc_rs1_eq_sp,

    rvc_rs1_eq_x0,

    rvc_rs2_eq_x0,

    rvc_rd_ne_x0_x2,

    rvc_rd_ne_x0,

    rvc_rs1_ne_x0,

    rvc_rs2_ne_x0,

    rvc_rs2_eq_rs1,

    rvc_rs1_eq_ra,

    rvc_imm_eq_zero,
@@ -2522,111 +2499,16 @@ static bool check_constraints(rv_decode *dec, const rvc_constraint *c) 
    uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2;

    while (*c != rvc_end) {

        switch (*c) {

        case rvc_simm_6:

            if (!(imm >= -32 && imm < 32)) {

                return false;

            }

            break;

        case rvc_imm_6:

            if (!(imm <= 63)) {

                return false;

            }

            break;

        case rvc_imm_7:

            if (!(imm <= 127)) {

                return false;

            }

            break;

        case rvc_imm_8:

            if (!(imm <= 255)) {

                return false;

            }

            break;

        case rvc_imm_9:

            if (!(imm <= 511)) {

                return false;

            }

            break;

        case rvc_imm_10:

            if (!(imm <= 1023)) {

                return false;

            }

            break;

        case rvc_imm_12:

            if (!(imm <= 4095)) {

                return false;

            }

            break;

        case rvc_imm_18:

            if (!(imm <= 262143)) {

                return false;

            }

            break;

        case rvc_imm_nz:

            if (!(imm != 0)) {

                return false;

            }

            break;

        case rvc_imm_x2:

            if (!((imm & 0b1) == 0)) {

                return false;

            }

            break;

        case rvc_imm_x4:

            if (!((imm & 0b11) == 0)) {

                return false;

            }

            break;

        case rvc_imm_x8:

            if (!((imm & 0b111) == 0)) {

                return false;

            }

            break;

        case rvc_imm_x16:

            if (!((imm & 0b1111) == 0)) {

                return false;

            }

            break;

        case rvc_rd_b3:

            if (!(rd  >= 8 && rd  <= 15)) {

                return false;

            }

            break;

        case rvc_rs1_b3:

            if (!(rs1 >= 8 && rs1 <= 15)) {

                return false;

            }

            break;

        case rvc_rs2_b3:

            if (!(rs2 >= 8 && rs2 <= 15)) {

                return false;

            }

            break;

        case rvc_rd_eq_rs1:

            if (!(rd == rs1)) {

                return false;

            }

            break;

        case rvc_rd_eq_ra:

            if (!(rd == 1)) {

                return false;

            }

            break;

        case rvc_rd_eq_sp:

            if (!(rd == 2)) {

                return false;

            }

            break;

        case rvc_rd_eq_x0:

            if (!(rd == 0)) {

                return false;

            }

            break;

        case rvc_rs1_eq_sp:

            if (!(rs1 == 2)) {

                return false;

            }

            break;

        case rvc_rs1_eq_x0:

            if (!(rs1 == 0)) {

                return false;
@@ -2637,26 +2519,6 @@ static bool check_constraints(rv_decode *dec, const rvc_constraint *c) 
                return false;

            }

            break;

        case rvc_rd_ne_x0_x2:

            if (!(rd != 0 && rd != 2)) {

                return false;

            }

            break;

        case rvc_rd_ne_x0:

            if (!(rd != 0)) {

                return false;

            }

            break;

        case rvc_rs1_ne_x0:

            if (!(rs1 != 0)) {

                return false;

            }

            break;

        case rvc_rs2_ne_x0:

            if (!(rs2 != 0)) {

                return false;

            }

            break;

        case rvc_rs2_eq_rs1:

            if (!(rs2 == rs1)) {

                return false;

gdb-xml/riscv-32bit-cpu.xml

0 → 100644
+47 −0
Original line number Diff line number Diff line 
<?xml version="1.0"?>

<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.



     Copying and distribution of this file, with or without modification,

     are permitted in any medium without royalty provided the copyright

     notice and this notice are preserved.  -->



<!-- Register numbers are hard-coded in order to maintain backward

     compatibility with older versions of tools that didn't use xml

     register descriptions.  -->



<!DOCTYPE feature SYSTEM "gdb-target.dtd">

<feature name="org.gnu.gdb.riscv.cpu">

  <reg name="zero" bitsize="32" type="int" regnum="0"/>

  <reg name="ra" bitsize="32" type="code_ptr"/>

  <reg name="sp" bitsize="32" type="data_ptr"/>

  <reg name="gp" bitsize="32" type="data_ptr"/>

  <reg name="tp" bitsize="32" type="data_ptr"/>

  <reg name="t0" bitsize="32" type="int"/>

  <reg name="t1" bitsize="32" type="int"/>

  <reg name="t2" bitsize="32" type="int"/>

  <reg name="fp" bitsize="32" type="data_ptr"/>

  <reg name="s1" bitsize="32" type="int"/>

  <reg name="a0" bitsize="32" type="int"/>

  <reg name="a1" bitsize="32" type="int"/>

  <reg name="a2" bitsize="32" type="int"/>

  <reg name="a3" bitsize="32" type="int"/>

  <reg name="a4" bitsize="32" type="int"/>

  <reg name="a5" bitsize="32" type="int"/>

  <reg name="a6" bitsize="32" type="int"/>

  <reg name="a7" bitsize="32" type="int"/>

  <reg name="s2" bitsize="32" type="int"/>

  <reg name="s3" bitsize="32" type="int"/>

  <reg name="s4" bitsize="32" type="int"/>

  <reg name="s5" bitsize="32" type="int"/>

  <reg name="s6" bitsize="32" type="int"/>

  <reg name="s7" bitsize="32" type="int"/>

  <reg name="s8" bitsize="32" type="int"/>

  <reg name="s9" bitsize="32" type="int"/>

  <reg name="s10" bitsize="32" type="int"/>

  <reg name="s11" bitsize="32" type="int"/>

  <reg name="t3" bitsize="32" type="int"/>

  <reg name="t4" bitsize="32" type="int"/>

  <reg name="t5" bitsize="32" type="int"/>

  <reg name="t6" bitsize="32" type="int"/>

  <reg name="pc" bitsize="32" type="code_ptr"/>

</feature>

gdb-xml/riscv-32bit-csr.xml

0 → 100644
+250 −0
Original line number Diff line number Diff line 
<?xml version="1.0"?>

<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.



     Copying and distribution of this file, with or without modification,

     are permitted in any medium without royalty provided the copyright

     notice and this notice are preserved.  -->



<!DOCTYPE feature SYSTEM "gdb-target.dtd">

<feature name="org.gnu.gdb.riscv.csr">

  <reg name="ustatus" bitsize="32"/>

  <reg name="uie" bitsize="32"/>

  <reg name="utvec" bitsize="32"/>

  <reg name="uscratch" bitsize="32"/>

  <reg name="uepc" bitsize="32"/>

  <reg name="ucause" bitsize="32"/>

  <reg name="utval" bitsize="32"/>

  <reg name="uip" bitsize="32"/>

  <reg name="fflags" bitsize="32"/>

  <reg name="frm" bitsize="32"/>

  <reg name="fcsr" bitsize="32"/>

  <reg name="cycle" bitsize="32"/>

  <reg name="time" bitsize="32"/>

  <reg name="instret" bitsize="32"/>

  <reg name="hpmcounter3" bitsize="32"/>

  <reg name="hpmcounter4" bitsize="32"/>

  <reg name="hpmcounter5" bitsize="32"/>

  <reg name="hpmcounter6" bitsize="32"/>

  <reg name="hpmcounter7" bitsize="32"/>

  <reg name="hpmcounter8" bitsize="32"/>

  <reg name="hpmcounter9" bitsize="32"/>

  <reg name="hpmcounter10" bitsize="32"/>

  <reg name="hpmcounter11" bitsize="32"/>

  <reg name="hpmcounter12" bitsize="32"/>

  <reg name="hpmcounter13" bitsize="32"/>

  <reg name="hpmcounter14" bitsize="32"/>

  <reg name="hpmcounter15" bitsize="32"/>

  <reg name="hpmcounter16" bitsize="32"/>

  <reg name="hpmcounter17" bitsize="32"/>

  <reg name="hpmcounter18" bitsize="32"/>

  <reg name="hpmcounter19" bitsize="32"/>

  <reg name="hpmcounter20" bitsize="32"/>

  <reg name="hpmcounter21" bitsize="32"/>

  <reg name="hpmcounter22" bitsize="32"/>

  <reg name="hpmcounter23" bitsize="32"/>

  <reg name="hpmcounter24" bitsize="32"/>

  <reg name="hpmcounter25" bitsize="32"/>

  <reg name="hpmcounter26" bitsize="32"/>

  <reg name="hpmcounter27" bitsize="32"/>

  <reg name="hpmcounter28" bitsize="32"/>

  <reg name="hpmcounter29" bitsize="32"/>

  <reg name="hpmcounter30" bitsize="32"/>

  <reg name="hpmcounter31" bitsize="32"/>

  <reg name="cycleh" bitsize="32"/>

  <reg name="timeh" bitsize="32"/>

  <reg name="instreth" bitsize="32"/>

  <reg name="hpmcounter3h" bitsize="32"/>

  <reg name="hpmcounter4h" bitsize="32"/>

  <reg name="hpmcounter5h" bitsize="32"/>

  <reg name="hpmcounter6h" bitsize="32"/>

  <reg name="hpmcounter7h" bitsize="32"/>

  <reg name="hpmcounter8h" bitsize="32"/>

  <reg name="hpmcounter9h" bitsize="32"/>

  <reg name="hpmcounter10h" bitsize="32"/>

  <reg name="hpmcounter11h" bitsize="32"/>

  <reg name="hpmcounter12h" bitsize="32"/>

  <reg name="hpmcounter13h" bitsize="32"/>

  <reg name="hpmcounter14h" bitsize="32"/>

  <reg name="hpmcounter15h" bitsize="32"/>

  <reg name="hpmcounter16h" bitsize="32"/>

  <reg name="hpmcounter17h" bitsize="32"/>

  <reg name="hpmcounter18h" bitsize="32"/>

  <reg name="hpmcounter19h" bitsize="32"/>

  <reg name="hpmcounter20h" bitsize="32"/>

  <reg name="hpmcounter21h" bitsize="32"/>

  <reg name="hpmcounter22h" bitsize="32"/>

  <reg name="hpmcounter23h" bitsize="32"/>

  <reg name="hpmcounter24h" bitsize="32"/>

  <reg name="hpmcounter25h" bitsize="32"/>

  <reg name="hpmcounter26h" bitsize="32"/>

  <reg name="hpmcounter27h" bitsize="32"/>

  <reg name="hpmcounter28h" bitsize="32"/>

  <reg name="hpmcounter29h" bitsize="32"/>

  <reg name="hpmcounter30h" bitsize="32"/>

  <reg name="hpmcounter31h" bitsize="32"/>

  <reg name="sstatus" bitsize="32"/>

  <reg name="sedeleg" bitsize="32"/>

  <reg name="sideleg" bitsize="32"/>

  <reg name="sie" bitsize="32"/>

  <reg name="stvec" bitsize="32"/>

  <reg name="scounteren" bitsize="32"/>

  <reg name="sscratch" bitsize="32"/>

  <reg name="sepc" bitsize="32"/>

  <reg name="scause" bitsize="32"/>

  <reg name="stval" bitsize="32"/>

  <reg name="sip" bitsize="32"/>

  <reg name="satp" bitsize="32"/>

  <reg name="mvendorid" bitsize="32"/>

  <reg name="marchid" bitsize="32"/>

  <reg name="mimpid" bitsize="32"/>

  <reg name="mhartid" bitsize="32"/>

  <reg name="mstatus" bitsize="32"/>

  <reg name="misa" bitsize="32"/>

  <reg name="medeleg" bitsize="32"/>

  <reg name="mideleg" bitsize="32"/>

  <reg name="mie" bitsize="32"/>

  <reg name="mtvec" bitsize="32"/>

  <reg name="mcounteren" bitsize="32"/>

  <reg name="mscratch" bitsize="32"/>

  <reg name="mepc" bitsize="32"/>

  <reg name="mcause" bitsize="32"/>

  <reg name="mtval" bitsize="32"/>

  <reg name="mip" bitsize="32"/>

  <reg name="pmpcfg0" bitsize="32"/>

  <reg name="pmpcfg1" bitsize="32"/>

  <reg name="pmpcfg2" bitsize="32"/>

  <reg name="pmpcfg3" bitsize="32"/>

  <reg name="pmpaddr0" bitsize="32"/>

  <reg name="pmpaddr1" bitsize="32"/>

  <reg name="pmpaddr2" bitsize="32"/>

  <reg name="pmpaddr3" bitsize="32"/>

  <reg name="pmpaddr4" bitsize="32"/>

  <reg name="pmpaddr5" bitsize="32"/>

  <reg name="pmpaddr6" bitsize="32"/>

  <reg name="pmpaddr7" bitsize="32"/>

  <reg name="pmpaddr8" bitsize="32"/>

  <reg name="pmpaddr9" bitsize="32"/>

  <reg name="pmpaddr10" bitsize="32"/>

  <reg name="pmpaddr11" bitsize="32"/>

  <reg name="pmpaddr12" bitsize="32"/>

  <reg name="pmpaddr13" bitsize="32"/>

  <reg name="pmpaddr14" bitsize="32"/>

  <reg name="pmpaddr15" bitsize="32"/>

  <reg name="mcycle" bitsize="32"/>

  <reg name="minstret" bitsize="32"/>

  <reg name="mhpmcounter3" bitsize="32"/>

  <reg name="mhpmcounter4" bitsize="32"/>

  <reg name="mhpmcounter5" bitsize="32"/>

  <reg name="mhpmcounter6" bitsize="32"/>

  <reg name="mhpmcounter7" bitsize="32"/>

  <reg name="mhpmcounter8" bitsize="32"/>

  <reg name="mhpmcounter9" bitsize="32"/>

  <reg name="mhpmcounter10" bitsize="32"/>

  <reg name="mhpmcounter11" bitsize="32"/>

  <reg name="mhpmcounter12" bitsize="32"/>

  <reg name="mhpmcounter13" bitsize="32"/>

  <reg name="mhpmcounter14" bitsize="32"/>

  <reg name="mhpmcounter15" bitsize="32"/>

  <reg name="mhpmcounter16" bitsize="32"/>

  <reg name="mhpmcounter17" bitsize="32"/>

  <reg name="mhpmcounter18" bitsize="32"/>

  <reg name="mhpmcounter19" bitsize="32"/>

  <reg name="mhpmcounter20" bitsize="32"/>

  <reg name="mhpmcounter21" bitsize="32"/>

  <reg name="mhpmcounter22" bitsize="32"/>

  <reg name="mhpmcounter23" bitsize="32"/>

  <reg name="mhpmcounter24" bitsize="32"/>

  <reg name="mhpmcounter25" bitsize="32"/>

  <reg name="mhpmcounter26" bitsize="32"/>

  <reg name="mhpmcounter27" bitsize="32"/>

  <reg name="mhpmcounter28" bitsize="32"/>

  <reg name="mhpmcounter29" bitsize="32"/>

  <reg name="mhpmcounter30" bitsize="32"/>

  <reg name="mhpmcounter31" bitsize="32"/>

  <reg name="mcycleh" bitsize="32"/>

  <reg name="minstreth" bitsize="32"/>

  <reg name="mhpmcounter3h" bitsize="32"/>

  <reg name="mhpmcounter4h" bitsize="32"/>

  <reg name="mhpmcounter5h" bitsize="32"/>

  <reg name="mhpmcounter6h" bitsize="32"/>

  <reg name="mhpmcounter7h" bitsize="32"/>

  <reg name="mhpmcounter8h" bitsize="32"/>

  <reg name="mhpmcounter9h" bitsize="32"/>

  <reg name="mhpmcounter10h" bitsize="32"/>

  <reg name="mhpmcounter11h" bitsize="32"/>

  <reg name="mhpmcounter12h" bitsize="32"/>

  <reg name="mhpmcounter13h" bitsize="32"/>

  <reg name="mhpmcounter14h" bitsize="32"/>

  <reg name="mhpmcounter15h" bitsize="32"/>

  <reg name="mhpmcounter16h" bitsize="32"/>

  <reg name="mhpmcounter17h" bitsize="32"/>

  <reg name="mhpmcounter18h" bitsize="32"/>

  <reg name="mhpmcounter19h" bitsize="32"/>

  <reg name="mhpmcounter20h" bitsize="32"/>

  <reg name="mhpmcounter21h" bitsize="32"/>

  <reg name="mhpmcounter22h" bitsize="32"/>

  <reg name="mhpmcounter23h" bitsize="32"/>

  <reg name="mhpmcounter24h" bitsize="32"/>

  <reg name="mhpmcounter25h" bitsize="32"/>

  <reg name="mhpmcounter26h" bitsize="32"/>

  <reg name="mhpmcounter27h" bitsize="32"/>

  <reg name="mhpmcounter28h" bitsize="32"/>

  <reg name="mhpmcounter29h" bitsize="32"/>

  <reg name="mhpmcounter30h" bitsize="32"/>

  <reg name="mhpmcounter31h" bitsize="32"/>

  <reg name="mhpmevent3" bitsize="32"/>

  <reg name="mhpmevent4" bitsize="32"/>

  <reg name="mhpmevent5" bitsize="32"/>

  <reg name="mhpmevent6" bitsize="32"/>

  <reg name="mhpmevent7" bitsize="32"/>

  <reg name="mhpmevent8" bitsize="32"/>

  <reg name="mhpmevent9" bitsize="32"/>

  <reg name="mhpmevent10" bitsize="32"/>

  <reg name="mhpmevent11" bitsize="32"/>

  <reg name="mhpmevent12" bitsize="32"/>

  <reg name="mhpmevent13" bitsize="32"/>

  <reg name="mhpmevent14" bitsize="32"/>

  <reg name="mhpmevent15" bitsize="32"/>

  <reg name="mhpmevent16" bitsize="32"/>

  <reg name="mhpmevent17" bitsize="32"/>

  <reg name="mhpmevent18" bitsize="32"/>

  <reg name="mhpmevent19" bitsize="32"/>

  <reg name="mhpmevent20" bitsize="32"/>

  <reg name="mhpmevent21" bitsize="32"/>

  <reg name="mhpmevent22" bitsize="32"/>

  <reg name="mhpmevent23" bitsize="32"/>

  <reg name="mhpmevent24" bitsize="32"/>

  <reg name="mhpmevent25" bitsize="32"/>

  <reg name="mhpmevent26" bitsize="32"/>

  <reg name="mhpmevent27" bitsize="32"/>

  <reg name="mhpmevent28" bitsize="32"/>

  <reg name="mhpmevent29" bitsize="32"/>

  <reg name="mhpmevent30" bitsize="32"/>

  <reg name="mhpmevent31" bitsize="32"/>

  <reg name="tselect" bitsize="32"/>

  <reg name="tdata1" bitsize="32"/>

  <reg name="tdata2" bitsize="32"/>

  <reg name="tdata3" bitsize="32"/>

  <reg name="dcsr" bitsize="32"/>

  <reg name="dpc" bitsize="32"/>

  <reg name="dscratch" bitsize="32"/>

  <reg name="hstatus" bitsize="32"/>

  <reg name="hedeleg" bitsize="32"/>

  <reg name="hideleg" bitsize="32"/>

  <reg name="hie" bitsize="32"/>

  <reg name="htvec" bitsize="32"/>

  <reg name="hscratch" bitsize="32"/>

  <reg name="hepc" bitsize="32"/>

  <reg name="hcause" bitsize="32"/>

  <reg name="hbadaddr" bitsize="32"/>

  <reg name="hip" bitsize="32"/>

  <reg name="mbase" bitsize="32"/>

  <reg name="mbound" bitsize="32"/>

  <reg name="mibase" bitsize="32"/>

  <reg name="mibound" bitsize="32"/>

  <reg name="mdbase" bitsize="32"/>

  <reg name="mdbound" bitsize="32"/>

  <reg name="mucounteren" bitsize="32"/>

  <reg name="mscounteren" bitsize="32"/>

  <reg name="mhcounteren" bitsize="32"/>

</feature>