Commit b8f5171c authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Implement FP data-processing (2 source) for fp16 



We missed all of the scalar fp16 binary operations.

Cc: qemu-stable@nongnu.org
Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Tested-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Message-id: 20180512003217.9105-7-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 3d99d931

target/arm/translate-a64.c

+65 −0
Original line number Diff line number Diff line
@@ -5299,6 +5299,61 @@ static void handle_fp_2src_double(DisasContext *s, int opcode, 
    tcg_temp_free_i64(tcg_res);

}



/* Floating-point data-processing (2 source) - half precision */

static void handle_fp_2src_half(DisasContext *s, int opcode,

                                int rd, int rn, int rm)

{

    TCGv_i32 tcg_op1;

    TCGv_i32 tcg_op2;

    TCGv_i32 tcg_res;

    TCGv_ptr fpst;



    tcg_res = tcg_temp_new_i32();

    fpst = get_fpstatus_ptr(true);

    tcg_op1 = read_fp_hreg(s, rn);

    tcg_op2 = read_fp_hreg(s, rm);



    switch (opcode) {

    case 0x0: /* FMUL */

        gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);

        break;

    case 0x1: /* FDIV */

        gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);

        break;

    case 0x2: /* FADD */

        gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);

        break;

    case 0x3: /* FSUB */

        gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);

        break;

    case 0x4: /* FMAX */

        gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);

        break;

    case 0x5: /* FMIN */

        gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);

        break;

    case 0x6: /* FMAXNM */

        gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);

        break;

    case 0x7: /* FMINNM */

        gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);

        break;

    case 0x8: /* FNMUL */

        gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);

        tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);

        break;

    default:

        g_assert_not_reached();

    }



    write_fp_sreg(s, rd, tcg_res);



    tcg_temp_free_ptr(fpst);

    tcg_temp_free_i32(tcg_op1);

    tcg_temp_free_i32(tcg_op2);

    tcg_temp_free_i32(tcg_res);

}



/* Floating point data-processing (2 source)

 *   31  30  29 28       24 23  22  21 20  16 15    12 11 10 9    5 4    0

 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
@@ -5331,6 +5386,16 @@ static void disas_fp_2src(DisasContext *s, uint32_t insn) 
        }

        handle_fp_2src_double(s, opcode, rd, rn, rm);

        break;

    case 3:

        if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

            unallocated_encoding(s);

            return;

        }

        if (!fp_access_check(s)) {

            return;

        }

        handle_fp_2src_half(s, opcode, rd, rn, rm);

        break;

    default:

        unallocated_encoding(s);

    }