Commit b6cd0ea1 authored by Aurelien Jarno's avatar Aurelien Jarno
Browse files

8250: Customized base baudrate 

(Jan Kiszka)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4336 c046a42c-6fe2-441c-8c8c-71466251a162
parent 6936bfe5

hw/mips_jazz.c

+2 −2
Original line number Diff line number Diff line
@@ -234,9 +234,9 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size, 


    /* Serial ports */

    if (serial_hds[0])

        serial_mm_init(0x80006000, 0, rc4030[8], serial_hds[0], 1);

        serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1);

    if (serial_hds[1])

        serial_mm_init(0x80007000, 0, rc4030[9], serial_hds[1], 1);

        serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1);



    /* Parallel port */

    if (parallel_hds[0])

hw/mips_malta.c

+4 −3
Original line number Diff line number Diff line
@@ -449,7 +449,8 @@ static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env) 


    uart_chr = qemu_chr_open("vc:80Cx24C");

    qemu_chr_printf(uart_chr, "CBUS UART\r\n");

    s->uart = serial_mm_init(base + 0x900, 3, env->irq[2], uart_chr, 1);

    s->uart =

        serial_mm_init(base + 0x900, 3, env->irq[2], 230400, uart_chr, 1);



    malta_fpga_reset(s);

    qemu_register_reset(malta_fpga_reset, s);
@@ -918,9 +919,9 @@ void mips_malta_init (ram_addr_t ram_size, int vga_ram_size, 
    i8042_init(i8259[1], i8259[12], 0x60);

    rtc_state = rtc_init(0x70, i8259[8]);

    if (serial_hds[0])

        serial_init(0x3f8, i8259[4], serial_hds[0]);

        serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);

    if (serial_hds[1])

        serial_init(0x2f8, i8259[3], serial_hds[1]);

        serial_init(0x2f8, i8259[3], 115200, serial_hds[1]);

    if (parallel_hds[0])

        parallel_init(0x378, i8259[7], parallel_hds[0]);

    for(i = 0; i < MAX_FD; i++) {

hw/mips_mipssim.c

+1 −1
Original line number Diff line number Diff line
@@ -174,7 +174,7 @@ mips_mipssim_init (ram_addr_t ram_size, int vga_ram_size, 
    /* A single 16450 sits at offset 0x3f8. It is attached to

       MIPS CPU INT2, which is interrupt 4. */

    if (serial_hds[0])

        serial_init(0x3f8, env->irq[4], serial_hds[0]);

        serial_init(0x3f8, env->irq[4], 115200, serial_hds[0]);



    if (nd_table[0].vlan) {

        if (nd_table[0].model == NULL

hw/mips_r4k.c

+2 −1
Original line number Diff line number Diff line
@@ -241,7 +241,8 @@ void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size, 


    for(i = 0; i < MAX_SERIAL_PORTS; i++) {

        if (serial_hds[i]) {

            serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]);

            serial_init(serial_io[i], i8259[serial_irq[i]], 115200,

                        serial_hds[i]);

        }

    }

hw/musicpal.c

+2 −2
Original line number Diff line number Diff line
@@ -1448,10 +1448,10 @@ static void musicpal_init(ram_addr_t ram_size, int vga_ram_size, 
    mv88w8618_pit_init(MP_PIT_BASE, pic, MP_TIMER1_IRQ);



    if (serial_hds[0])

        serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], /*1825000,*/

        serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,

                   serial_hds[0], 1);

    if (serial_hds[1])

        serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], /*1825000,*/

        serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,

                   serial_hds[1], 1);



    /* Register flash */