Commit b635d98c authored by Philippe Mathieu-Daudé's avatar Philippe Mathieu-Daudé Committed by Peter Maydell
Browse files

sdhci: use DEFINE_SDHCI_COMMON_PROPERTIES() for common sysbus/pci properties 



Add common/sysbus/pci/sdbus comments to have clearer code blocks separation.

Signed-off-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180115182436.2066-4-f4bug@amsat.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 03603958

hw/sd/sdhci.c

+17 −8
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
 */



#include "qemu/osdep.h"

#include "qapi/error.h"

#include "hw/hw.h"

#include "sysemu/block-backend.h"

#include "sysemu/blockdev.h"
@@ -1185,6 +1186,14 @@ static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 
    }

}



/* --- qdev common --- */



#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \

    /* Capabilities registers provide information on supported features

     * of this specific host controller implementation */ \

    DEFINE_PROP_UINT32("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \

    DEFINE_PROP_UINT32("maxcurr", _state, maxcurr, 0)



static void sdhci_initfn(SDHCIState *s)

{

    qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
@@ -1264,12 +1273,10 @@ const VMStateDescription sdhci_vmstate = { 
    },

};



/* Capabilities registers provide information on supported features of this

 * specific host controller implementation */

/* --- qdev PCI --- */



static Property sdhci_pci_properties[] = {

    DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,

            SDHC_CAPAB_REG_DEFAULT),

    DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),

    DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState),

    DEFINE_PROP_END_OF_LIST(),

};
@@ -1320,10 +1327,10 @@ static const TypeInfo sdhci_pci_info = { 
    },

};



/* --- qdev SysBus --- */



static Property sdhci_sysbus_properties[] = {

    DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,

            SDHC_CAPAB_REG_DEFAULT),

    DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),

    DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState),

    DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,

                     false),

    DEFINE_PROP_END_OF_LIST(),
@@ -1374,6 +1381,8 @@ static const TypeInfo sdhci_sysbus_info = { 
    .class_init = sdhci_sysbus_class_init,

};



/* --- qdev bus master --- */



static void sdhci_bus_class_init(ObjectClass *klass, void *data)

{

    SDBusClass *sbc = SD_BUS_CLASS(klass);

include/hw/sd/sdhci.h

+3 −1
Original line number Diff line number Diff line
@@ -79,13 +79,15 @@ typedef struct SDHCIState { 
    uint32_t buf_maxsz;

    uint16_t data_count;   /* current element in FIFO buffer */

    uint8_t  stopped_state;/* Current SDHC state */

    bool     pending_insert_quirk;/* Quirk for Raspberry Pi card insert int */

    bool     pending_insert_state;

    /* Buffer Data Port Register - virtual access point to R and W buffers */

    /* Software Reset Register - always reads as 0 */

    /* Force Event Auto CMD12 Error Interrupt Reg - write only */

    /* Force Event Error Interrupt Register- write only */

    /* RO Host Controller Version Register always reads as 0x2401 */



    /* Configurable properties */

    bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */

} SDHCIState;



#define TYPE_PCI_SDHCI "sdhci-pci"