Commit b5ff1b31 authored by Fabrice Bellard's avatar Fabrice Bellard
Browse files

ARM system emulation (Paul Brook) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1661 c046a42c-6fe2-441c-8c8c-71466251a162
parent 0e43e99c

Changelog

+3 −1
Original line number Diff line number Diff line 
version 0.7.3:



  - ARM system emulation: Arm Integrator/CP board with an arm1026ej-s

    cpu (Paul Brook)

  - SMP support

  - Mac OS X cocoa improvements (Mike Kronenberg)

  - Mac OS X CoreAudio driver (Mike Kronenberg)

  - DirectSound driver (malc)
@@ -10,7 +13,6 @@ version 0.7.3: 
  - Linux host serial port access

  - Linux host low level parallel port access

  - New network emulation code supporting VLANs.

  - SMP support



version 0.7.2:

Makefile.target

+4 −1
Original line number Diff line number Diff line
@@ -211,7 +211,7 @@ LIBOBJS+= op_helper.o helper.o 
endif



ifeq ($(TARGET_BASE_ARCH), arm)

LIBOBJS+= op_helper.o

LIBOBJS+= op_helper.o helper.o

endif



# NOTE: the disassembler code is only needed for debugging
@@ -324,6 +324,9 @@ VL_OBJS+= sun4m.o tcx.o lance.o iommu.o m48t59.o magic-load.o slavio_intctl.o 
VL_OBJS+= slavio_timer.o slavio_serial.o slavio_misc.o fdc.o esp.o

endif

endif

ifeq ($(TARGET_BASE_ARCH), arm)

VL_OBJS+= integratorcp.o ps2.o

endif

ifdef CONFIG_GDBSTUB

VL_OBJS+=gdbstub.o 

endif

configure

+1 −1
Original line number Diff line number Diff line
@@ -227,7 +227,7 @@ fi 


if test -z "$target_list" ; then

# these targets are portable

    target_list="i386-softmmu ppc-softmmu sparc-softmmu x86_64-softmmu mips-softmmu"

    target_list="i386-softmmu ppc-softmmu sparc-softmmu x86_64-softmmu mips-softmmu arm-softmmu"

# the following are Linux specific

    if [ "$linux" = "yes" ] ; then

        target_list="i386-user arm-user armeb-user sparc-user ppc-user $target_list"

cpu-exec.c

+18 −15
Original line number Diff line number Diff line
@@ -173,6 +173,8 @@ static inline TranslationBlock *tb_find_fast(void) 
#elif defined(TARGET_ARM)

    flags = env->thumb | (env->vfp.vec_len << 1)

            | (env->vfp.vec_stride << 4);

    if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)

        flags |= (1 << 6);

    cs_base = 0;

    pc = env->regs[15];

#elif defined(TARGET_SPARC)
@@ -322,15 +324,6 @@ int cpu_exec(CPUState *env1) 
    CC_OP = CC_OP_EFLAGS;

    env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);

#elif defined(TARGET_ARM)

    {

        unsigned int psr;

        psr = env->cpsr;

        env->CF = (psr >> 29) & 1;

        env->NZF = (psr & 0xc0000000) ^ 0x40000000;

        env->VF = (psr << 3) & 0x80000000;

        env->QF = (psr >> 27) & 1;

        env->cpsr = psr & ~CACHED_CPSR_BITS;

    }

#elif defined(TARGET_SPARC)

#if defined(reg_REGWPTR)

    saved_regwptr = REGWPTR;
@@ -379,6 +372,8 @@ int cpu_exec(CPUState *env1) 
                    do_interrupt(env);

#elif defined(TARGET_SPARC)

                    do_interrupt(env->exception_index);

#elif defined(TARGET_ARM)

                    do_interrupt(env);

#endif

                }

                env->exception_index = -1;
@@ -508,8 +503,19 @@ int cpu_exec(CPUState *env1) 
			//do_interrupt(0, 0, 0, 0, 0);

			env->interrupt_request &= ~CPU_INTERRUPT_TIMER;

		    }

#elif defined(TARGET_ARM)

                    if (interrupt_request & CPU_INTERRUPT_FIQ

                        && !(env->uncached_cpsr & CPSR_F)) {

                        env->exception_index = EXCP_FIQ;

                        do_interrupt(env);

                    }

                    if (interrupt_request & CPU_INTERRUPT_HARD

                        && !(env->uncached_cpsr & CPSR_I)) {

                        env->exception_index = EXCP_IRQ;

                        do_interrupt(env);

                    }

#endif

                    if (interrupt_request & CPU_INTERRUPT_EXITTB) {

                    if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {

                        env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;

                        /* ensure that no TB jump will be modified as

                           the program flow was changed */
@@ -526,7 +532,7 @@ int cpu_exec(CPUState *env1) 
                    }

                }

#ifdef DEBUG_EXEC

                if ((loglevel & CPU_LOG_EXEC)) {

                if ((loglevel & CPU_LOG_TB_CPU)) {

#if defined(TARGET_I386)

                    /* restore flags in standard format */

#ifdef reg_EAX
@@ -557,9 +563,7 @@ int cpu_exec(CPUState *env1) 
                    cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);

                    env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);

#elif defined(TARGET_ARM)

                    env->cpsr = compute_cpsr();

                    cpu_dump_state(env, logfile, fprintf, 0);

                    env->cpsr &= ~CACHED_CPSR_BITS;

#elif defined(TARGET_SPARC)

		    REGWPTR = env->regbase + (env->cwp * 16);

		    env->regwptr = REGWPTR;
@@ -760,7 +764,6 @@ int cpu_exec(CPUState *env1) 
    EDI = saved_EDI;

#endif

#elif defined(TARGET_ARM)

    env->cpsr = compute_cpsr();

    /* XXX: Save/restore host fpu exception state?.  */

#elif defined(TARGET_SPARC)

#if defined(reg_REGWPTR)

exec-all.h

+3 −1
Original line number Diff line number Diff line
@@ -549,8 +549,10 @@ static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) 
    is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);

#elif defined (TARGET_SPARC)

    is_user = (env->psrs == 0);

#elif defined (TARGET_ARM)

    is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR);

#else

#error "Unimplemented !"

#error unimplemented CPU

#endif

    if (__builtin_expect(env->tlb_read[is_user][index].address != 

                         (addr & TARGET_PAGE_MASK), 0)) {