Commit b5a12aa2 authored by Blue Swirl's avatar Blue Swirl
Browse files

Merge branch 'rth/vis2' of git://repo.or.cz/qemu/rth 

* 'rth/vis2' of git://repo.or.cz/qemu/rth:
  target-sparc: Implement FALIGNDATA inline.
  target-sparc: Implement BMASK/BSHUFFLE.
  target-sparc: Implement ALIGNADDR* inline.
  target-sparc: Implement EDGE* instructions.
  target-sparc: Implement fpack{16,32,fix}.
  target-sparc: Implement PDIST.
  target-sparc: Do exceptions management fully inside the helpers.
  target-sparc: Change fpr representation to doubles.
  target-sparc: Undo cpu_fpr rename.
  target-sparc: Extract float128 move to a function.
  target-sparc: Extract common code for floating-point operations.
  target-sparc: Make FPU/VIS helpers const when possible.
  target-sparc: Pass float64 parameters instead of dt0/1 temporaries.
  target-sparc: Add accessors for double-precision fpr access.
  target-sparc: Mark fprs dirty in store accessor.
  target-sparc: Add accessors for single-precision fpr access.
parents 9f60639b 50c796f9

gdbstub.c

+24 −11
Original line number Diff line number Diff line
@@ -814,7 +814,11 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) 
#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)

    if (n < 64) {

        /* fprs */

        GET_REG32(*((uint32_t *)&env->fpr[n - 32]));

        if (n & 1) {

            GET_REG32(env->fpr[(n - 32) / 2].l.lower);

        } else {

            GET_REG32(env->fpr[(n - 32) / 2].l.upper);

        }

    }

    /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */

    switch (n) {
@@ -831,15 +835,15 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) 
#else

    if (n < 64) {

        /* f0-f31 */

        GET_REG32(*((uint32_t *)&env->fpr[n - 32]));

        if (n & 1) {

            GET_REG32(env->fpr[(n - 32) / 2].l.lower);

        } else {

            GET_REG32(env->fpr[(n - 32) / 2].l.upper);

        }

    }

    if (n < 80) {

        /* f32-f62 (double width, even numbers only) */

        uint64_t val;



        val = (uint64_t)*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) << 32;

        val |= *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]);

        GET_REG64(val);

        GET_REG64(env->fpr[(n - 32) / 2].ll);

    }

    switch (n) {

    case 80: GET_REGL(env->pc);
@@ -878,7 +882,12 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) 
#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)

    else if (n < 64) {

        /* fprs */

        *((uint32_t *)&env->fpr[n - 32]) = tmp;

        /* f0-f31 */

        if (n & 1) {

            env->fpr[(n - 32) / 2].l.lower = tmp;

        } else {

            env->fpr[(n - 32) / 2].l.upper = tmp;

        }

    } else {

        /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */

        switch (n) {
@@ -896,12 +905,16 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) 
#else

    else if (n < 64) {

        /* f0-f31 */

        env->fpr[n] = ldfl_p(mem_buf);

        tmp = ldl_p(mem_buf);

        if (n & 1) {

            env->fpr[(n - 32) / 2].l.lower = tmp;

        } else {

            env->fpr[(n - 32) / 2].l.upper = tmp;

        }

        return 4;

    } else if (n < 80) {

        /* f32-f62 (double width, even numbers only) */

        *((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) = tmp >> 32;

        *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]) = tmp;

        env->fpr[(n - 32) / 2].ll = tmp;

    } else {

        switch (n) {

        case 80: env->pc = tmp; break;

linux-user/signal.c

+16 −12
Original line number Diff line number Diff line
@@ -2296,12 +2296,14 @@ void sparc64_set_context(CPUSPARCState *env) 
     */

    err |= __get_user(env->fprs, &(ucp->tuc_mcontext.mc_fpregs.mcfpu_fprs));

    {

        uint32_t *src, *dst;

        src = ucp->tuc_mcontext.mc_fpregs.mcfpu_fregs.sregs;

        dst = env->fpr;

        /* XXX: check that the CPU storage is the same as user context */

        for (i = 0; i < 64; i++, dst++, src++)

            err |= __get_user(*dst, src);

        uint32_t *src = ucp->tuc_mcontext.mc_fpregs.mcfpu_fregs.sregs;

        for (i = 0; i < 64; i++, src++) {

            if (i & 1) {

                err |= __get_user(env->fpr[i/2].l.lower, src);

            } else {

                err |= __get_user(env->fpr[i/2].l.upper, src);

            }

        }

    }

    err |= __get_user(env->fsr,

                      &(ucp->tuc_mcontext.mc_fpregs.mcfpu_fsr));
@@ -2390,12 +2392,14 @@ void sparc64_get_context(CPUSPARCState *env) 
    err |= __put_user(i7, &(mcp->mc_i7));



    {

        uint32_t *src, *dst;

        src = env->fpr;

        dst = ucp->tuc_mcontext.mc_fpregs.mcfpu_fregs.sregs;

        /* XXX: check that the CPU storage is the same as user context */

        for (i = 0; i < 64; i++, dst++, src++)

            err |= __put_user(*src, dst);

        uint32_t *dst = ucp->tuc_mcontext.mc_fpregs.mcfpu_fregs.sregs;

        for (i = 0; i < 64; i++, dst++) {

            if (i & 1) {

                err |= __put_user(env->fpr[i/2].l.lower, dst);

            } else {

                err |= __put_user(env->fpr[i/2].l.upper, dst);

            }

        }

    }

    err |= __put_user(env->fsr, &(mcp->mc_fpregs.mcfpu_fsr));

    err |= __put_user(env->gsr, &(mcp->mc_fpregs.mcfpu_gsr));

monitor.c

+48 −48
Original line number Diff line number Diff line
@@ -3471,55 +3471,55 @@ static const MonitorDef monitor_defs[] = { 
#endif

    { "tbr", offsetof(CPUState, tbr) },

    { "fsr", offsetof(CPUState, fsr) },

    { "f0", offsetof(CPUState, fpr[0]) },

    { "f1", offsetof(CPUState, fpr[1]) },

    { "f2", offsetof(CPUState, fpr[2]) },

    { "f3", offsetof(CPUState, fpr[3]) },

    { "f4", offsetof(CPUState, fpr[4]) },

    { "f5", offsetof(CPUState, fpr[5]) },

    { "f6", offsetof(CPUState, fpr[6]) },

    { "f7", offsetof(CPUState, fpr[7]) },

    { "f8", offsetof(CPUState, fpr[8]) },

    { "f9", offsetof(CPUState, fpr[9]) },

    { "f10", offsetof(CPUState, fpr[10]) },

    { "f11", offsetof(CPUState, fpr[11]) },

    { "f12", offsetof(CPUState, fpr[12]) },

    { "f13", offsetof(CPUState, fpr[13]) },

    { "f14", offsetof(CPUState, fpr[14]) },

    { "f15", offsetof(CPUState, fpr[15]) },

    { "f16", offsetof(CPUState, fpr[16]) },

    { "f17", offsetof(CPUState, fpr[17]) },

    { "f18", offsetof(CPUState, fpr[18]) },

    { "f19", offsetof(CPUState, fpr[19]) },

    { "f20", offsetof(CPUState, fpr[20]) },

    { "f21", offsetof(CPUState, fpr[21]) },

    { "f22", offsetof(CPUState, fpr[22]) },

    { "f23", offsetof(CPUState, fpr[23]) },

    { "f24", offsetof(CPUState, fpr[24]) },

    { "f25", offsetof(CPUState, fpr[25]) },

    { "f26", offsetof(CPUState, fpr[26]) },

    { "f27", offsetof(CPUState, fpr[27]) },

    { "f28", offsetof(CPUState, fpr[28]) },

    { "f29", offsetof(CPUState, fpr[29]) },

    { "f30", offsetof(CPUState, fpr[30]) },

    { "f31", offsetof(CPUState, fpr[31]) },

    { "f0", offsetof(CPUState, fpr[0].l.upper) },

    { "f1", offsetof(CPUState, fpr[0].l.lower) },

    { "f2", offsetof(CPUState, fpr[1].l.upper) },

    { "f3", offsetof(CPUState, fpr[1].l.lower) },

    { "f4", offsetof(CPUState, fpr[2].l.upper) },

    { "f5", offsetof(CPUState, fpr[2].l.lower) },

    { "f6", offsetof(CPUState, fpr[3].l.upper) },

    { "f7", offsetof(CPUState, fpr[3].l.lower) },

    { "f8", offsetof(CPUState, fpr[4].l.upper) },

    { "f9", offsetof(CPUState, fpr[4].l.lower) },

    { "f10", offsetof(CPUState, fpr[5].l.upper) },

    { "f11", offsetof(CPUState, fpr[5].l.lower) },

    { "f12", offsetof(CPUState, fpr[6].l.upper) },

    { "f13", offsetof(CPUState, fpr[6].l.lower) },

    { "f14", offsetof(CPUState, fpr[7].l.upper) },

    { "f15", offsetof(CPUState, fpr[7].l.lower) },

    { "f16", offsetof(CPUState, fpr[8].l.upper) },

    { "f17", offsetof(CPUState, fpr[8].l.lower) },

    { "f18", offsetof(CPUState, fpr[9].l.upper) },

    { "f19", offsetof(CPUState, fpr[9].l.lower) },

    { "f20", offsetof(CPUState, fpr[10].l.upper) },

    { "f21", offsetof(CPUState, fpr[10].l.lower) },

    { "f22", offsetof(CPUState, fpr[11].l.upper) },

    { "f23", offsetof(CPUState, fpr[11].l.lower) },

    { "f24", offsetof(CPUState, fpr[12].l.upper) },

    { "f25", offsetof(CPUState, fpr[12].l.lower) },

    { "f26", offsetof(CPUState, fpr[13].l.upper) },

    { "f27", offsetof(CPUState, fpr[13].l.lower) },

    { "f28", offsetof(CPUState, fpr[14].l.upper) },

    { "f29", offsetof(CPUState, fpr[14].l.lower) },

    { "f30", offsetof(CPUState, fpr[15].l.upper) },

    { "f31", offsetof(CPUState, fpr[15].l.lower) },

#ifdef TARGET_SPARC64

    { "f32", offsetof(CPUState, fpr[32]) },

    { "f34", offsetof(CPUState, fpr[34]) },

    { "f36", offsetof(CPUState, fpr[36]) },

    { "f38", offsetof(CPUState, fpr[38]) },

    { "f40", offsetof(CPUState, fpr[40]) },

    { "f42", offsetof(CPUState, fpr[42]) },

    { "f44", offsetof(CPUState, fpr[44]) },

    { "f46", offsetof(CPUState, fpr[46]) },

    { "f48", offsetof(CPUState, fpr[48]) },

    { "f50", offsetof(CPUState, fpr[50]) },

    { "f52", offsetof(CPUState, fpr[52]) },

    { "f54", offsetof(CPUState, fpr[54]) },

    { "f56", offsetof(CPUState, fpr[56]) },

    { "f58", offsetof(CPUState, fpr[58]) },

    { "f60", offsetof(CPUState, fpr[60]) },

    { "f62", offsetof(CPUState, fpr[62]) },

    { "f32", offsetof(CPUState, fpr[16]) },

    { "f34", offsetof(CPUState, fpr[17]) },

    { "f36", offsetof(CPUState, fpr[18]) },

    { "f38", offsetof(CPUState, fpr[19]) },

    { "f40", offsetof(CPUState, fpr[20]) },

    { "f42", offsetof(CPUState, fpr[21]) },

    { "f44", offsetof(CPUState, fpr[22]) },

    { "f46", offsetof(CPUState, fpr[23]) },

    { "f48", offsetof(CPUState, fpr[24]) },

    { "f50", offsetof(CPUState, fpr[25]) },

    { "f52", offsetof(CPUState, fpr[26]) },

    { "f54", offsetof(CPUState, fpr[27]) },

    { "f56", offsetof(CPUState, fpr[28]) },

    { "f58", offsetof(CPUState, fpr[29]) },

    { "f60", offsetof(CPUState, fpr[30]) },

    { "f62", offsetof(CPUState, fpr[31]) },

    { "asi", offsetof(CPUState, asi) },

    { "pstate", offsetof(CPUState, pstate) },

    { "cansave", offsetof(CPUState, cansave) },

target-sparc/cpu.h

+4 −4
Original line number Diff line number Diff line
@@ -3,16 +3,17 @@ 


#include "config.h"

#include "qemu-common.h"

#include "bswap.h"



#if !defined(TARGET_SPARC64)

#define TARGET_LONG_BITS 32

#define TARGET_FPREGS 32

#define TARGET_DPREGS 16

#define TARGET_PAGE_BITS 12 /* 4k */

#define TARGET_PHYS_ADDR_SPACE_BITS 36

#define TARGET_VIRT_ADDR_SPACE_BITS 32

#else

#define TARGET_LONG_BITS 64

#define TARGET_FPREGS 64

#define TARGET_DPREGS 32

#define TARGET_PAGE_BITS 13 /* 8k */

#define TARGET_PHYS_ADDR_SPACE_BITS 41

# ifdef TARGET_ABI32
@@ -395,7 +396,7 @@ typedef struct CPUSPARCState { 


    uint32_t psr;      /* processor state register */

    target_ulong fsr;      /* FPU state register */

    float32 fpr[TARGET_FPREGS];  /* floating point registers */

    CPU_DoubleU fpr[TARGET_DPREGS];  /* floating point registers */

    uint32_t cwp;      /* index of current register window (extracted

                          from PSR) */

#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
@@ -463,7 +464,6 @@ typedef struct CPUSPARCState { 
    uint64_t prom_addr;

#endif

    /* temporary float registers */

    float64 dt0, dt1;

    float128 qt0, qt1;

    float_status fp_status;

#if defined(TARGET_SPARC64)

target-sparc/cpu_init.c

+3 −3
Original line number Diff line number Diff line
@@ -813,11 +813,11 @@ void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf, 
        }

    }

    cpu_fprintf(f, "\nFloating Point Registers:\n");

    for (i = 0; i < TARGET_FPREGS; i++) {

    for (i = 0; i < TARGET_DPREGS; i++) {

        if ((i & 3) == 0) {

            cpu_fprintf(f, "%%f%02d:", i);

            cpu_fprintf(f, "%%f%02d:", i * 2);

        }

        cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]);

        cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);

        if ((i & 3) == 3) {

            cpu_fprintf(f, "\n");

        }