Commit b4fbe1f6 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190129' into staging 



target-arm queue:
 * Fix validation of 32-bit address spaces for aa32 (fixes an assert introduced in ba97be9f)
 * v8m: Ensure IDAU is respected if SAU is disabled
 * gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0
 * exec.c: Use correct attrs in cpu_memory_rw_debug()
 * accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
 * target/arm: Don't clear supported PMU events when initializing PMCEID1
 * memory: add memory_region_flush_rom_device()
 * microbit: Add stub NRF51 TWI magnetometer/accelerometer detection
 * tests/microbit-test: extend testing of microbit devices
 * checkpatch: Don't emit spurious warnings about block comments
 * aspeed/smc: misc bug fixes
 * xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
 * xlnx-zynqmp: Realize cluster after putting RPUs in it
 * accel/tcg: Add cluster number to TCG TB hash so differently configured
   CPUs don't pick up cached TBs for the wrong kind of CPU

# gpg: Signature made Tue 29 Jan 2019 11:59:10 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190129: (23 commits)
  gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index
  accel/tcg: Add cluster number to TCG TB hash
  qom/cpu: Add cluster_index to CPUState
  hw/arm/xlnx-zynqmp: Realize cluster after putting RPUs in it
  aspeed/smc: snoop SPI transfers to fake dummy cycles
  aspeed/smc: Add dummy data register
  aspeed/smc: define registers for all possible CS
  aspeed/smc: fix default read value
  xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
  checkpatch: Don't emit spurious warnings about block comments
  tests/microbit-test: Check nRF51 UART functionality
  tests/microbit-test: Make test independent of global_qtest
  tests/libqtest: Introduce qtest_init_with_serial()
  memory: add memory_region_flush_rom_device()
  target/arm: Don't clear supported PMU events when initializing PMCEID1
  MAINTAINERS: update microbit ARM board files
  accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
  exec.c: Use correct attrs in cpu_memory_rw_debug()
  tests/microbit-test: add TWI stub device test
  arm: Stub out NRF51 TWI magnetometer/accelerometer detection
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 3a183e33 46f5abc0

MAINTAINERS

+5 −3
Original line number Diff line number Diff line
@@ -829,9 +829,11 @@ M: Joel Stanley <joel@jms.id.au> 
M: Peter Maydell <peter.maydell@linaro.org>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/arm/nrf51_soc.c

F: hw/arm/microbit.c

F: include/hw/arm/nrf51_soc.h

F: hw/*/nrf51*.c

F: hw/*/microbit*.c

F: include/hw/*/nrf51*.h

F: include/hw/*/microbit*.h

F: tests/microbit-test.c



CRIS Machines

-------------

accel/tcg/cpu-exec.c

+3 −0
Original line number Diff line number Diff line
@@ -325,6 +325,9 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, 
    struct tb_desc desc;

    uint32_t h;



    cf_mask &= ~CF_CLUSTER_MASK;

    cf_mask |= cpu->cluster_index << CF_CLUSTER_SHIFT;



    desc.env = (CPUArchState *)cpu->env_ptr;

    desc.cs_base = cs_base;

    desc.flags = flags;

accel/tcg/translate-all.c

+3 −0
Original line number Diff line number Diff line
@@ -1688,6 +1688,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, 
        cflags |= CF_NOCACHE | 1;

    }



    cflags &= ~CF_CLUSTER_MASK;

    cflags |= cpu->cluster_index << CF_CLUSTER_SHIFT;



 buffer_overflow:

    tb = tb_alloc(pc);

    if (unlikely(!tb)) {

accel/tcg/user-exec.c

+52 −14
Original line number Diff line number Diff line
@@ -479,15 +479,53 @@ int cpu_signal_handler(int host_signum, void *pinfo, 


#elif defined(__aarch64__)



#ifndef ESR_MAGIC

/* Pre-3.16 kernel headers don't have these, so provide fallback definitions */

#define ESR_MAGIC 0x45535201

struct esr_context {

    struct _aarch64_ctx head;

    uint64_t esr;

};

#endif



static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc)

{

    return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved;

}



static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr)

{

    return (struct _aarch64_ctx *)((char *)hdr + hdr->size);

}



int cpu_signal_handler(int host_signum, void *pinfo, void *puc)

{

    siginfo_t *info = pinfo;

    ucontext_t *uc = puc;

    uintptr_t pc = uc->uc_mcontext.pc;

    uint32_t insn = *(uint32_t *)pc;

    bool is_write;

    struct _aarch64_ctx *hdr;

    struct esr_context const *esrctx = NULL;



    /* Find the esr_context, which has the WnR bit in it */

    for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) {

        if (hdr->magic == ESR_MAGIC) {

            esrctx = (struct esr_context const *)hdr;

            break;

        }

    }



    if (esrctx) {

        /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */

        uint64_t esr = esrctx->esr;

        is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1;

    } else {

        /*

         * Fall back to parsing instructions; will only be needed

         * for really ancient (pre-3.16) kernels.

         */

        uint32_t insn = *(uint32_t *)pc;



    /* XXX: need kernel patch to get write flag faster.  */

        is_write = ((insn & 0xbfff0000) == 0x0c000000   /* C3.3.1 */

                    || (insn & 0xbfe00000) == 0x0c800000   /* C3.3.2 */

                    || (insn & 0xbfdf0000) == 0x0d000000   /* C3.3.3 */
@@ -495,12 +533,12 @@ int cpu_signal_handler(int host_signum, void *pinfo, void *puc) 
                    || (insn & 0x3f400000) == 0x08000000   /* C3.3.6 */

                    || (insn & 0x3bc00000) == 0x39000000   /* C3.3.13 */

                    || (insn & 0x3fc00000) == 0x3d800000   /* ... 128bit */

                /* Ingore bits 10, 11 & 21, controlling indexing.  */

                    /* Ignore bits 10, 11 & 21, controlling indexing.  */

                    || (insn & 0x3bc00000) == 0x38000000   /* C3.3.8-12 */

                    || (insn & 0x3fe00000) == 0x3c800000   /* ... 128bit */

                    /* Ignore bits 23 & 24, controlling indexing.  */

                    || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */



    }

    return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);

}

exec.c

+15 −4
Original line number Diff line number Diff line
@@ -3162,6 +3162,19 @@ static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr, 
    cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);

}



void memory_region_flush_rom_device(MemoryRegion *mr, hwaddr addr, hwaddr size)

{

    /*

     * In principle this function would work on other memory region types too,

     * but the ROM device use case is the only one where this operation is

     * necessary.  Other memory regions should use the

     * address_space_read/write() APIs.

     */

    assert(memory_region_is_romd(mr));



    invalidate_and_set_dirty(mr, addr, size);

}



static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)

{

    unsigned access_size_max = mr->ops->valid.max_access_size;
@@ -3882,12 +3895,10 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, 
        phys_addr += (addr & ~TARGET_PAGE_MASK);

        if (is_write) {

            address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr,

                                    MEMTXATTRS_UNSPECIFIED,

                                    buf, l);

                                    attrs, buf, l);

        } else {

            address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,

                             MEMTXATTRS_UNSPECIFIED,

                             buf, l, 0);

                             attrs, buf, l, 0);

        }

        len -= l;

        buf += l;