Commit b49572d3 authored by Richard Henderson's avatar Richard Henderson
Browse files

target/hppa: Implement a pause instruction 



This is an extension to the base ISA, but we can use this in
the kernel idle loop to reduce the host cpu time consumed.

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent 2330504c

target/hppa/translate.c

+36 −0
Original line number Diff line number Diff line
@@ -2826,9 +2826,45 @@ static DisasJumpType trans_ds(DisasContext *ctx, uint32_t insn, 
    return nullify_end(ctx, DISAS_NEXT);

}



#ifndef CONFIG_USER_ONLY

/* These are QEMU extensions and are nops in the real architecture:

 *

 * or %r10,%r10,%r10 -- idle loop; wait for interrupt

 * or %r31,%r31,%r31 -- death loop; offline cpu

 *                      currently implemented as idle.

 */

static DisasJumpType trans_pause(DisasContext *ctx, uint32_t insn,

                                 const DisasInsn *di)

{

    TCGv_i32 tmp;



    /* No need to check for supervisor, as userland can only pause

       until the next timer interrupt.  */

    nullify_over(ctx);



    /* Advance the instruction queue.  */

    copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b);

    copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var);

    nullify_set(ctx, 0);



    /* Tell the qemu main loop to halt until this cpu has work.  */

    tmp = tcg_const_i32(1);

    tcg_gen_st_i32(tmp, cpu_env, -offsetof(HPPACPU, env) +

                                 offsetof(CPUState, halted));

    tcg_temp_free_i32(tmp);

    gen_excp_1(EXCP_HALTED);



    return nullify_end(ctx, DISAS_NORETURN);

}

#endif



static const DisasInsn table_arith_log[] = {

    { 0x08000240u, 0xfc00ffffu, trans_nop },  /* or x,y,0 */

    { 0x08000240u, 0xffe0ffe0u, trans_copy }, /* or x,0,t */

#ifndef CONFIG_USER_ONLY

    { 0x094a024au, 0xffffffffu, trans_pause }, /* or r10,r10,r10 */

    { 0x0bff025fu, 0xffffffffu, trans_pause }, /* or r31,r31,r31 */

#endif

    { 0x08000000u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_andc_reg },

    { 0x08000200u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_and_reg },

    { 0x08000240u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_or_reg },