Loading target-m68k/translate.c +11 −9 Original line number Diff line number Diff line Loading @@ -865,19 +865,21 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) DISAS_INSN(scc) { TCGLabel *l1; DisasCompare c; int cond; TCGv reg; TCGv reg, tmp; l1 = gen_new_label(); cond = (insn >> 8) & 0xf; gen_cc_cond(&c, s, cond); tmp = tcg_temp_new(); tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2); free_cond(&c); reg = DREG(insn, 0); tcg_gen_andi_i32(reg, reg, 0xffffff00); /* This is safe because we modify the reg directly, with no other values live. */ gen_jmpcc(s, cond ^ 1, l1); tcg_gen_ori_i32(reg, reg, 0xff); gen_set_label(l1); tcg_gen_neg_i32(tmp, tmp); tcg_gen_deposit_i32(reg, reg, tmp, 0, 8); tcg_temp_free(tmp); } /* Force a TB lookup after an instruction that changes the CPU state. */ Loading Loading
target-m68k/translate.c +11 −9 Original line number Diff line number Diff line Loading @@ -865,19 +865,21 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) DISAS_INSN(scc) { TCGLabel *l1; DisasCompare c; int cond; TCGv reg; TCGv reg, tmp; l1 = gen_new_label(); cond = (insn >> 8) & 0xf; gen_cc_cond(&c, s, cond); tmp = tcg_temp_new(); tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2); free_cond(&c); reg = DREG(insn, 0); tcg_gen_andi_i32(reg, reg, 0xffffff00); /* This is safe because we modify the reg directly, with no other values live. */ gen_jmpcc(s, cond ^ 1, l1); tcg_gen_ori_i32(reg, reg, 0xff); gen_set_label(l1); tcg_gen_neg_i32(tmp, tmp); tcg_gen_deposit_i32(reg, reg, tmp, 0, 8); tcg_temp_free(tmp); } /* Force a TB lookup after an instruction that changes the CPU state. */ Loading