Commit b3e54c68 authored by Blue Swirl's avatar Blue Swirl
Browse files

Merge branch 'xtensa' of git://jcmvbkbc.spb.ru/dumb/qemu-xtensa 

* 'xtensa' of git://jcmvbkbc.spb.ru/dumb/qemu-xtensa:
  target-xtensa: add breakpoint tests
  target-xtensa: add DEBUG_SECTION to overlay tool
  target-xtensa: add DBREAK data breakpoints
  exec: let cpu_watchpoint_insert accept larger watchpoints
  exec: fix check_watchpoint exiting cpu_loop
  exec: add missing breaks to the watch_mem_write
  target-xtensa: add ICOUNT SR and debug exception
  target-xtensa: implement instruction breakpoints
  target-xtensa: add DEBUGCAUSE SR and configuration
  target-xtensa: fetch 3rd opcode byte only when needed
  target-xtensa: implement info tlb monitor command
  target-xtensa: define TLB_TEMPLATE for MMU-less cores
parents 88e6c606 e7dfa64d

exec.c

+13 −5
Original line number Diff line number Diff line
@@ -1504,7 +1504,8 @@ int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, 
    CPUWatchpoint *wp;



    /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */

    if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) {

    if ((len & (len - 1)) || (addr & ~len_mask) ||

            len == 0 || len > TARGET_PAGE_SIZE) {

        fprintf(stderr, "qemu: tried to set invalid watchpoint at "

                TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len);

        return -EINVAL;
@@ -3331,12 +3332,13 @@ static void check_watchpoint(int offset, int len_mask, int flags) 
                tb_phys_invalidate(tb, -1);

                if (wp->flags & BP_STOP_BEFORE_ACCESS) {

                    env->exception_index = EXCP_DEBUG;

                    cpu_loop_exit(env);

                } else {

                    cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);

                    tb_gen_code(env, pc, cs_base, cpu_flags, 1);

                }

                    cpu_resume_from_signal(env, NULL);

                }

            }

        } else {

            wp->flags &= ~BP_WATCHPOINT_HIT;

        }
@@ -3363,9 +3365,15 @@ static void watch_mem_write(void *opaque, target_phys_addr_t addr, 
{

    check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);

    switch (size) {

    case 1: stb_phys(addr, val);

    case 2: stw_phys(addr, val);

    case 4: stl_phys(addr, val);

    case 1:

        stb_phys(addr, val);

        break;

    case 2:

        stw_phys(addr, val);

        break;

    case 4:

        stl_phys(addr, val);

        break;

    default: abort();

    }

}

hmp-commands.hx

+1 −1
Original line number Diff line number Diff line
@@ -1355,7 +1355,7 @@ show i8259 (PIC) state 
@item info pci

show emulated PCI device info

@item info tlb

show virtual to physical memory mappings (i386, SH4, SPARC, and PPC only)

show virtual to physical memory mappings (i386, SH4, SPARC, PPC, and Xtensa only)

@item info mem

show the active virtual memory mappings (i386 only)

@item info jit

monitor.c

+2 −2
Original line number Diff line number Diff line
@@ -1949,7 +1949,7 @@ static void tlb_info(Monitor *mon) 


#endif



#if defined(TARGET_SPARC) || defined(TARGET_PPC)

#if defined(TARGET_SPARC) || defined(TARGET_PPC) || defined(TARGET_XTENSA)

static void tlb_info(Monitor *mon)

{

    CPUState *env1 = mon_get_cpu();
@@ -2396,7 +2396,7 @@ static mon_cmd_t info_cmds[] = { 
        .mhandler.info = hmp_info_pci,

    },

#if defined(TARGET_I386) || defined(TARGET_SH4) || defined(TARGET_SPARC) || \

    defined(TARGET_PPC)

    defined(TARGET_PPC) || defined(TARGET_XTENSA)

    {

        .name       = "tlb",

        .args_type  = "",

target-xtensa/core-dc232b.c

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ static const XtensaConfig dc232b = { 
    EXCEPTIONS_SECTION,

    INTERRUPTS_SECTION,

    TLB_SECTION,

    DEBUG_SECTION,

    .clock_freq_khz = 10000,

};

target-xtensa/core-fsf.c

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ static const XtensaConfig fsf = { 
    EXCEPTIONS_SECTION,

    INTERRUPTS_SECTION,

    TLB_SECTION,

    DEBUG_SECTION,

    .clock_freq_khz = 10000,

};