Commit b3a1179f authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170907' into staging 



TCG constant pools

# gpg: Signature made Thu 07 Sep 2017 23:35:45 BST
# gpg:                using RSA key 0x64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20170907: (23 commits)
  tcg/ppc: Use constant pool for movi
  tcg/ppc: Look for shifted constants
  tcg/ppc: Change TCG_REG_RA to TCG_REG_TB
  tcg/arm: Use constant pool for call
  tcg/arm: Use constant pool for movi
  tcg/arm: Extract INSN_NOP
  tcg/arm: Code rearrangement
  tcg/arm: Tighten tlb indexing offset test
  tcg/arm: Improve tlb load for armv7
  tcg/sparc: Use constant pool for movi
  tcg/sparc: Introduce TCG_REG_TB
  tcg/aarch64: Use constant pool for movi
  tcg/s390: Use constant pool for cmpi
  tcg/s390: Use constant pool for xori
  tcg/s390: Use constant pool for ori
  tcg/s390: Use constant pool for andi
  tcg/s390: Use constant pool for movi
  tcg/s390: Fix sign of patch_reloc addend
  tcg/s390: Introduce TCG_REG_TB
  tcg/i386: Store out-of-range call targets in constant pool
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents e6d767b7 53c89efd

accel/tcg/cpu-exec.c

+35 −0
Original line number Diff line number Diff line
@@ -329,6 +329,41 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, 
    return qht_lookup(&tcg_ctx.tb_ctx.htable, tb_cmp, &desc, h);

}



void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr)

{

    if (TCG_TARGET_HAS_direct_jump) {

        uintptr_t offset = tb->jmp_target_arg[n];

        uintptr_t tc_ptr = (uintptr_t)tb->tc_ptr;

        tb_target_set_jmp_target(tc_ptr, tc_ptr + offset, addr);

    } else {

        tb->jmp_target_arg[n] = addr;

    }

}



/* Called with tb_lock held.  */

static inline void tb_add_jump(TranslationBlock *tb, int n,

                               TranslationBlock *tb_next)

{

    assert(n < ARRAY_SIZE(tb->jmp_list_next));

    if (tb->jmp_list_next[n]) {

        /* Another thread has already done this while we were

         * outside of the lock; nothing to do in this case */

        return;

    }

    qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,

                           "Linking TBs %p [" TARGET_FMT_lx

                           "] index %d -> %p [" TARGET_FMT_lx "]\n",

                           tb->tc_ptr, tb->pc, n,

                           tb_next->tc_ptr, tb_next->pc);



    /* patch the native jump address */

    tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);



    /* add in TB jmp circular list */

    tb->jmp_list_next[n] = tb_next->jmp_list_first;

    tb_next->jmp_list_first = (uintptr_t)tb | n;

}



static inline TranslationBlock *tb_find(CPUState *cpu,

                                        TranslationBlock *last_tb,

                                        int tb_exit)

accel/tcg/translate-all.c

+28 −8
Original line number Diff line number Diff line
@@ -1289,13 +1289,13 @@ TranslationBlock *tb_gen_code(CPUState *cpu, 
    tb->jmp_reset_offset[0] = TB_JMP_RESET_OFFSET_INVALID;

    tb->jmp_reset_offset[1] = TB_JMP_RESET_OFFSET_INVALID;

    tcg_ctx.tb_jmp_reset_offset = tb->jmp_reset_offset;

#ifdef USE_DIRECT_JUMP

    tcg_ctx.tb_jmp_insn_offset = tb->jmp_insn_offset;

    if (TCG_TARGET_HAS_direct_jump) {

        tcg_ctx.tb_jmp_insn_offset = tb->jmp_target_arg;

        tcg_ctx.tb_jmp_target_addr = NULL;

#else

    } else {

        tcg_ctx.tb_jmp_insn_offset = NULL;

    tcg_ctx.tb_jmp_target_addr = tb->jmp_target_addr;

#endif

        tcg_ctx.tb_jmp_target_addr = tb->jmp_target_arg;

    }



#ifdef CONFIG_PROFILER

    tcg_ctx.tb_count++;
@@ -1329,7 +1329,27 @@ TranslationBlock *tb_gen_code(CPUState *cpu, 
        qemu_log_in_addr_range(tb->pc)) {

        qemu_log_lock();

        qemu_log("OUT: [size=%d]\n", gen_code_size);

        if (tcg_ctx.data_gen_ptr) {

            size_t code_size = tcg_ctx.data_gen_ptr - tb->tc_ptr;

            size_t data_size = gen_code_size - code_size;

            size_t i;



            log_disas(tb->tc_ptr, code_size);



            for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) {

                if (sizeof(tcg_target_ulong) == 8) {

                    qemu_log("0x%08" PRIxPTR ":  .quad  0x%016" PRIx64 "\n",

                             (uintptr_t)tcg_ctx.data_gen_ptr + i,

                             *(uint64_t *)(tcg_ctx.data_gen_ptr + i));

                } else {

                    qemu_log("0x%08" PRIxPTR ":  .long  0x%08x\n",

                             (uintptr_t)tcg_ctx.data_gen_ptr + i,

                             *(uint32_t *)(tcg_ctx.data_gen_ptr + i));

                }

            }

        } else {

            log_disas(tb->tc_ptr, gen_code_size);

        }

        qemu_log("\n");

        qemu_log_flush();

        qemu_log_unlock();

include/elf.h

+2 −1
Original line number Diff line number Diff line
@@ -942,8 +942,9 @@ typedef struct { 
#define R_390_TLS_DTPOFF	55	/* Offset in TLS block.  */

#define R_390_TLS_TPOFF		56	/* Negate offset in static TLS

                                           block.  */

#define R_390_20                57

/* Keep this the last entry.  */

#define R_390_NUM	57

#define R_390_NUM               58



/* x86-64 relocation types */

#define R_X86_64_NONE		0	/* No reloc */

include/exec/exec-all.h

+3 −92
Original line number Diff line number Diff line
@@ -301,15 +301,6 @@ static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) 
#define CODE_GEN_AVG_BLOCK_SIZE 150

#endif



#if defined(_ARCH_PPC) \

    || defined(__x86_64__) || defined(__i386__) \

    || defined(__sparc__) || defined(__aarch64__) \

    || defined(__s390x__) || defined(__mips__) \

    || defined(CONFIG_TCG_INTERPRETER)

/* NOTE: Direct jump patching must be atomic to be thread-safe. */

#define USE_DIRECT_JUMP

#endif



struct TranslationBlock {

    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */

    target_ulong cs_base; /* CS base for this block */
@@ -347,11 +338,8 @@ struct TranslationBlock { 
     */

    uint16_t jmp_reset_offset[2]; /* offset of original jump target */

#define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */

#ifdef USE_DIRECT_JUMP

    uint16_t jmp_insn_offset[2]; /* offset of native jump instruction */

#else

    uintptr_t jmp_target_addr[2]; /* target address for indirect jump */

#endif

    uintptr_t jmp_target_arg[2];  /* target address or offset */



    /* Each TB has an assosiated circular list of TBs jumping to this one.

     * jmp_list_first points to the first TB jumping to this one.

     * jmp_list_next is used to point to the next TB in a list.
@@ -373,84 +361,7 @@ void tb_flush(CPUState *cpu); 
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);

TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,

                                   target_ulong cs_base, uint32_t flags);



#if defined(USE_DIRECT_JUMP)



#if defined(CONFIG_TCG_INTERPRETER)

static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)

{

    /* patch the branch destination */

    atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4));

    /* no need to flush icache explicitly */

}

#elif defined(_ARCH_PPC)

void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);

#define tb_set_jmp_target1 ppc_tb_set_jmp_target

#elif defined(__i386__) || defined(__x86_64__)

static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)

{

    /* patch the branch destination */

    atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4));

    /* no need to flush icache explicitly */

}

#elif defined(__s390x__)

static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)

{

    /* patch the branch destination */

    intptr_t disp = addr - (jmp_addr - 2);

    atomic_set((int32_t *)jmp_addr, disp / 2);

    /* no need to flush icache explicitly */

}

#elif defined(__aarch64__)

void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);

#define tb_set_jmp_target1 aarch64_tb_set_jmp_target

#elif defined(__sparc__) || defined(__mips__)

void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);

#else

#error tb_set_jmp_target1 is missing

#endif



static inline void tb_set_jmp_target(TranslationBlock *tb,

                                     int n, uintptr_t addr)

{

    uint16_t offset = tb->jmp_insn_offset[n];

    tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);

}



#else



/* set the jump target */

static inline void tb_set_jmp_target(TranslationBlock *tb,

                                     int n, uintptr_t addr)

{

    tb->jmp_target_addr[n] = addr;

}



#endif



/* Called with tb_lock held.  */

static inline void tb_add_jump(TranslationBlock *tb, int n,

                               TranslationBlock *tb_next)

{

    assert(n < ARRAY_SIZE(tb->jmp_list_next));

    if (tb->jmp_list_next[n]) {

        /* Another thread has already done this while we were

         * outside of the lock; nothing to do in this case */

        return;

    }

    qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,

                           "Linking TBs %p [" TARGET_FMT_lx

                           "] index %d -> %p [" TARGET_FMT_lx "]\n",

                           tb->tc_ptr, tb->pc, n,

                           tb_next->tc_ptr, tb_next->pc);



    /* patch the native jump address */

    tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);



    /* add in TB jmp circular list */

    tb->jmp_list_next[n] = tb_next->jmp_list_first;

    tb_next->jmp_list_first = (uintptr_t)tb | n;

}

void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);



/* GETPC is the true target of the return instruction that we'll execute.  */

#if defined(CONFIG_TCG_INTERPRETER)

tcg/aarch64/tcg-target.h

+9 −1
Original line number Diff line number Diff line
@@ -111,12 +111,20 @@ typedef enum { 
#define TCG_TARGET_HAS_muls2_i64        0

#define TCG_TARGET_HAS_muluh_i64        1

#define TCG_TARGET_HAS_mulsh_i64        1

#define TCG_TARGET_HAS_direct_jump      1



#define TCG_TARGET_DEFAULT_MO (0)



static inline void flush_icache_range(uintptr_t start, uintptr_t stop)

{

    __builtin___clear_cache((char *)start, (char *)stop);

}



#define TCG_TARGET_DEFAULT_MO (0)

void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);



#ifdef CONFIG_SOFTMMU

#define TCG_TARGET_NEED_LDST_LABELS

#endif

#define TCG_TARGET_NEED_POOL_LABELS



#endif /* AARCH64_TCG_TARGET_H */