Commit b35aec85 authored by Richard Henderson's avatar Richard Henderson
Browse files

target/hppa: Optimize blr r0,rn 



We can eliminate an extra TB in this case, which merely
loads a "return address" into rn.

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent 993119fe

target/hppa/translate.c

+10 −6
Original line number Diff line number Diff line
@@ -3488,12 +3488,16 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) 


static bool trans_blr(DisasContext *ctx, arg_blr *a)

{

    if (a->x) {

        TCGv_reg tmp = get_temp(ctx);



        tcg_gen_shli_reg(tmp, load_gpr(ctx, a->x), 3);

        tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8);

        /* The computation here never changes privilege level.  */

        return do_ibranch(ctx, tmp, a->l, a->n);

    } else {

        /* BLR R0,RX is a good way to load PC+8 into RX.  */

        return do_dbranch(ctx, ctx->iaoq_f + 8, a->l, a->n);

    }

}



static bool trans_bv(DisasContext *ctx, arg_bv *a)