Commit b1eb20da authored by Richard Henderson's avatar Richard Henderson
Browse files

tcg/aarch64: Fix addsub2 for 0+C 



When al == xzr, we cannot use addi/subi because that encodes xsp.
Force a zero into the temp register for that (rare) case.

Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
Message-Id: <20161207180727.6286-2-rth@twiddle.net>
parent 86c9ab27

tcg/aarch64/tcg-target.inc.c

+9 −0
Original line number Diff line number Diff line
@@ -964,6 +964,15 @@ static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl, 
            insn = I3401_SUBSI;

            bl = -bl;

        }

        if (unlikely(al == TCG_REG_XZR)) {

            /* ??? We want to allow al to be zero for the benefit of

               negation via subtraction.  However, that leaves open the

               possibility of adding 0+const in the low part, and the

               immediate add instructions encode XSP not XZR.  Don't try

               anything more elaborate here than loading another zero.  */

            al = TCG_REG_TMP;

            tcg_out_movi(s, ext, al, 0);

        }

        tcg_out_insn_3401(s, insn, ext, rl, al, bl);

    } else {

        tcg_out_insn_3502(s, sub ? I3502_SUBS : I3502_ADDS, ext, rl, al, bl);