Commit b0a19803 authored by Tao Xu's avatar Tao Xu Committed by Eduardo Habkost
Browse files

i386: Update stepping of Cascadelake-Server 



Update the stepping from 5 to 6, in order that
the Cascadelake-Server CPU model can support AVX512VNNI
and MSR based features exposed by ARCH_CAPABILITIES.

Signed-off-by: default avatarTao Xu <tao3.xu@intel.com>
Message-Id: <20181227024304.12182-2-tao3.xu@intel.com>
Signed-off-by: default avatarEduardo Habkost <ehabkost@redhat.com>
parent 5f39a91d

hw/i386/pc.c

+1 −0
Original line number Diff line number Diff line
@@ -122,6 +122,7 @@ GlobalProperty pc_compat_3_1[] = { 
    { "Cascadelake-Server" "-" TYPE_X86_CPU,  "mpx", "on" },

    { "Icelake-Client" "-" TYPE_X86_CPU,      "mpx", "on" },

    { "Icelake-Server" "-" TYPE_X86_CPU,      "mpx", "on" },

    { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },

};

const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);

target/i386/cpu.c

+1 −1
Original line number Diff line number Diff line
@@ -2503,7 +2503,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 
        .vendor = CPUID_VENDOR_INTEL,

        .family = 6,

        .model = 85,

        .stepping = 5,

        .stepping = 6,

        .features[FEAT_1_EDX] =

            CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |

            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |