Commit afb6e204 authored by BALATON Zoltan's avatar BALATON Zoltan Committed by David Gibson
Browse files

ppc4xx_i2c: Rewrite to model hardware more closely 



Rewrite to make it closer to how real device works so that guest OS
drivers can access I2C devices. Previously this was only a hack to
allow U-Boot to get past accessing SPD EEPROMs but to support other
I2C devices and allow guests to access them we need to model real
device more properly.

Signed-off-by: default avatarBALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: default avatarCédric Le Goater <clg@kaod.org>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 3c47beb8

hw/i2c/ppc4xx_i2c.c

+157 −142
Original line number Diff line number Diff line
@@ -34,16 +34,50 @@ 


#define PPC4xx_I2C_MEM_SIZE 18



enum {

    IIC_MDBUF = 0,

    /* IIC_SDBUF = 2, */

    IIC_LMADR = 4,

    IIC_HMADR,

    IIC_CNTL,

    IIC_MDCNTL,

    IIC_STS,

    IIC_EXTSTS,

    IIC_LSADR,

    IIC_HSADR,

    IIC_CLKDIV,

    IIC_INTRMSK,

    IIC_XFRCNT,

    IIC_XTCNTLSS,

    IIC_DIRECTCNTL

    /* IIC_INTR */

};



#define IIC_CNTL_PT         (1 << 0)

#define IIC_CNTL_READ       (1 << 1)

#define IIC_CNTL_CHT        (1 << 2)

#define IIC_CNTL_RPST       (1 << 3)

#define IIC_CNTL_AMD        (1 << 6)

#define IIC_CNTL_HMT        (1 << 7)



#define IIC_MDCNTL_EINT     (1 << 2)

#define IIC_MDCNTL_ESM      (1 << 3)

#define IIC_MDCNTL_FMDB     (1 << 6)



#define IIC_STS_PT          (1 << 0)

#define IIC_STS_IRQA        (1 << 1)

#define IIC_STS_ERR         (1 << 2)

#define IIC_STS_MDBF        (1 << 4)

#define IIC_STS_MDBS        (1 << 5)



#define IIC_EXTSTS_XFRA     (1 << 0)

#define IIC_EXTSTS_BCS_FREE (4 << 4)

#define IIC_EXTSTS_BCS_BUSY (5 << 4)



#define IIC_INTRMSK_EIMTC   (1 << 0)

#define IIC_INTRMSK_EITA    (1 << 1)

#define IIC_INTRMSK_EIIC    (1 << 2)

#define IIC_INTRMSK_EIHE    (1 << 3)



#define IIC_XTCNTLSS_SRST   (1 << 0)
@@ -56,130 +90,83 @@ static void ppc4xx_i2c_reset(DeviceState *s) 
{

    PPC4xxI2CState *i2c = PPC4xx_I2C(s);



    /* FIXME: Should also reset bus?

     *if (s->address != ADDR_RESET) {

     *    i2c_end_transfer(s->bus);

     *}

     */



    i2c->mdata = 0;

    i2c->lmadr = 0;

    i2c->hmadr = 0;

    i2c->mdidx = -1;

    memset(i2c->mdata, 0, ARRAY_SIZE(i2c->mdata));

    /* [hl][ms]addr are not affected by reset */

    i2c->cntl = 0;

    i2c->mdcntl = 0;

    i2c->sts = 0;

    i2c->extsts = 0x8f;

    i2c->lsadr = 0;

    i2c->hsadr = 0;

    i2c->extsts = IIC_EXTSTS_BCS_FREE;

    i2c->clkdiv = 0;

    i2c->intrmsk = 0;

    i2c->xfrcnt = 0;

    i2c->xtcntlss = 0;

    i2c->directcntl = 0xf;

}



static inline bool ppc4xx_i2c_is_master(PPC4xxI2CState *i2c)

{

    return true;

    i2c->directcntl = 0xf; /* all non-reserved bits set */

}



static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int size)

{

    PPC4xxI2CState *i2c = PPC4xx_I2C(opaque);

    uint64_t ret;

    int i;



    switch (addr) {

    case 0:

        ret = i2c->mdata;

        if (ppc4xx_i2c_is_master(i2c)) {

    case IIC_MDBUF:

        if (i2c->mdidx < 0) {

            ret = 0xff;



            if (!(i2c->sts & IIC_STS_MDBS)) {

                qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read "

                              "without starting transfer\n",

                              TYPE_PPC4xx_I2C, __func__);

            } else {

                int pending = (i2c->cntl >> 4) & 3;



                /* get the next byte */

                int byte = i2c_recv(i2c->bus);



                if (byte < 0) {

                    qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: read failed "

                                  "for device 0x%02x\n", TYPE_PPC4xx_I2C,

                                  __func__, i2c->lmadr);

                    ret = 0xff;

                } else {

                    ret = byte;

                    /* Raise interrupt if enabled */

                    /*ppc4xx_i2c_raise_interrupt(i2c)*/;

            break;

        }



                if (!pending) {

        ret = i2c->mdata[0];

        if (i2c->mdidx == 3) {

            i2c->sts &= ~IIC_STS_MDBF;

        } else if (i2c->mdidx == 0) {

            i2c->sts &= ~IIC_STS_MDBS;

                    /*i2c_end_transfer(i2c->bus);*/

                /*} else if (i2c->cntl & (IIC_CNTL_RPST | IIC_CNTL_CHT)) {*/

                } else if (pending) {

                    /* current smbus implementation doesn't like

                       multibyte xfer repeated start */

                    i2c_end_transfer(i2c->bus);

                    if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) {

                        /* if non zero is returned, the adress is not valid */

                        i2c->sts &= ~IIC_STS_PT;

                        i2c->sts |= IIC_STS_ERR;

                        i2c->extsts |= IIC_EXTSTS_XFRA;

                    } else {

                        /*i2c->sts |= IIC_STS_PT;*/

                        i2c->sts |= IIC_STS_MDBS;

                        i2c->sts &= ~IIC_STS_ERR;

                        i2c->extsts = 0;

        }

        for (i = 0; i < i2c->mdidx; i++) {

            i2c->mdata[i] = i2c->mdata[i + 1];

        }

                pending--;

                i2c->cntl = (i2c->cntl & 0xcf) | (pending << 4);

            }

        } else {

            qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n",

                          TYPE_PPC4xx_I2C, __func__);

        if (i2c->mdidx >= 0) {

            i2c->mdidx--;

        }

        break;

    case 4:

    case IIC_LMADR:

        ret = i2c->lmadr;

        break;

    case 5:

    case IIC_HMADR:

        ret = i2c->hmadr;

        break;

    case 6:

    case IIC_CNTL:

        ret = i2c->cntl;

        break;

    case 7:

    case IIC_MDCNTL:

        ret = i2c->mdcntl;

        break;

    case 8:

    case IIC_STS:

        ret = i2c->sts;

        break;

    case 9:

        ret = i2c->extsts;

    case IIC_EXTSTS:

        ret = i2c_bus_busy(i2c->bus) ?

              IIC_EXTSTS_BCS_BUSY : IIC_EXTSTS_BCS_FREE;

        break;

    case 10:

    case IIC_LSADR:

        ret = i2c->lsadr;

        break;

    case 11:

    case IIC_HSADR:

        ret = i2c->hsadr;

        break;

    case 12:

    case IIC_CLKDIV:

        ret = i2c->clkdiv;

        break;

    case 13:

    case IIC_INTRMSK:

        ret = i2c->intrmsk;

        break;

    case 14:

    case IIC_XFRCNT:

        ret = i2c->xfrcnt;

        break;

    case 15:

    case IIC_XTCNTLSS:

        ret = i2c->xtcntlss;

        break;

    case 16:

    case IIC_DIRECTCNTL:

        ret = i2c->directcntl;

        break;

    default:
@@ -202,99 +189,127 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value, 
    PPC4xxI2CState *i2c = opaque;



    switch (addr) {

    case 0:

        i2c->mdata = value;

    case IIC_MDBUF:

        if (i2c->mdidx >= 3) {

            break;

        }

        i2c->mdata[++i2c->mdidx] = value;

        if (i2c->mdidx == 3) {

            i2c->sts |= IIC_STS_MDBF;

        } else if (i2c->mdidx == 0) {

            i2c->sts |= IIC_STS_MDBS;

        }

        break;

    case IIC_LMADR:

        i2c->lmadr = value;

        break;

    case IIC_HMADR:

        i2c->hmadr = value;

        break;

    case IIC_CNTL:

        i2c->cntl = value & ~IIC_CNTL_PT;

        if (value & IIC_CNTL_AMD) {

            qemu_log_mask(LOG_UNIMP, "%s: only 7 bit addresses supported\n",

                          __func__);

        }

        if (value & IIC_CNTL_HMT && i2c_bus_busy(i2c->bus)) {

            i2c_end_transfer(i2c->bus);

            if (i2c->mdcntl & IIC_MDCNTL_EINT &&

                i2c->intrmsk & IIC_INTRMSK_EIHE) {

                i2c->sts |= IIC_STS_IRQA;

                qemu_irq_raise(i2c->irq);

            }

        } else if (value & IIC_CNTL_PT) {

            int recv = (value & IIC_CNTL_READ) >> 1;

            int tct = value >> 4 & 3;

            int i;



            if (recv && (i2c->lmadr >> 1) >= 0x50 && (i2c->lmadr >> 1) < 0x58) {

                /* smbus emulation does not like multi byte reads w/o restart */

                value |= IIC_CNTL_RPST;

            }



            for (i = 0; i <= tct; i++) {

                if (!i2c_bus_busy(i2c->bus)) {

            /* assume we start a write transfer */

            if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 0)) {

                /* if non zero is returned, the adress is not valid */

                i2c->sts &= ~IIC_STS_PT;

                    i2c->extsts = IIC_EXTSTS_BCS_FREE;

                    if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, recv)) {

                        i2c->sts |= IIC_STS_ERR;

                        i2c->extsts |= IIC_EXTSTS_XFRA;

                        break;

                    } else {

                i2c->sts |= IIC_STS_PT;

                        i2c->sts &= ~IIC_STS_ERR;

                i2c->extsts = 0;

                    }

                }

        if (i2c_bus_busy(i2c->bus)) {

            if (i2c_send(i2c->bus, i2c->mdata)) {

                /* if the target return non zero then end the transfer */

                i2c->sts &= ~IIC_STS_PT;

                if (!(i2c->sts & IIC_STS_ERR) &&

                    i2c_send_recv(i2c->bus, &i2c->mdata[i], !recv)) {

                    i2c->sts |= IIC_STS_ERR;

                    i2c->extsts |= IIC_EXTSTS_XFRA;

                i2c_end_transfer(i2c->bus);

            }

        }

                    break;

    case 4:

        i2c->lmadr = value;

        if (i2c_bus_busy(i2c->bus)) {

            i2c_end_transfer(i2c->bus);

                }

        break;

    case 5:

        i2c->hmadr = value;

        break;

    case 6:

        i2c->cntl = value;

        if (i2c->cntl & IIC_CNTL_PT) {

            if (i2c->cntl & IIC_CNTL_READ) {

                if (i2c_bus_busy(i2c->bus)) {

                    /* end previous transfer */

                    i2c->sts &= ~IIC_STS_PT;

                if (value & IIC_CNTL_RPST || !(value & IIC_CNTL_CHT)) {

                    i2c_end_transfer(i2c->bus);

                }

                if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) {

                    /* if non zero is returned, the adress is not valid */

                    i2c->sts &= ~IIC_STS_PT;

                    i2c->sts |= IIC_STS_ERR;

                    i2c->extsts |= IIC_EXTSTS_XFRA;

                } else {

                    /*i2c->sts |= IIC_STS_PT;*/

            }

            i2c->xfrcnt = i;

            i2c->mdidx = i - 1;

            if (recv && i2c->mdidx >= 0) {

                i2c->sts |= IIC_STS_MDBS;

                    i2c->sts &= ~IIC_STS_ERR;

                    i2c->extsts = 0;

            }

            } else {

                /* we actually already did the write transfer... */

                i2c->sts &= ~IIC_STS_PT;

            if (recv && i2c->mdidx == 3) {

                i2c->sts |= IIC_STS_MDBF;

            }

            if (i && i2c->mdcntl & IIC_MDCNTL_EINT &&

                i2c->intrmsk & IIC_INTRMSK_EIMTC) {

                i2c->sts |= IIC_STS_IRQA;

                qemu_irq_raise(i2c->irq);

            }

        }

        break;

    case 7:

        i2c->mdcntl = value & 0xdf;

    case IIC_MDCNTL:

        i2c->mdcntl = value & 0x3d;

        if (value & IIC_MDCNTL_ESM) {

            qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",

                          __func__);

        }

        if (value & IIC_MDCNTL_FMDB) {

            i2c->mdidx = -1;

            memset(i2c->mdata, 0, ARRAY_SIZE(i2c->mdata));

            i2c->sts &= ~(IIC_STS_MDBF | IIC_STS_MDBS);

        }

        break;

    case 8:

        i2c->sts &= ~(value & 0xa);

    case IIC_STS:

        i2c->sts &= ~(value & 0x0a);

        if (value & IIC_STS_IRQA && i2c->mdcntl & IIC_MDCNTL_EINT) {

            qemu_irq_lower(i2c->irq);

        }

        break;

    case 9:

    case IIC_EXTSTS:

        i2c->extsts &= ~(value & 0x8f);

        break;

    case 10:

    case IIC_LSADR:

        i2c->lsadr = value;

        break;

    case 11:

    case IIC_HSADR:

        i2c->hsadr = value;

        break;

    case 12:

    case IIC_CLKDIV:

        i2c->clkdiv = value;

        break;

    case 13:

    case IIC_INTRMSK:

        i2c->intrmsk = value;

        break;

    case 14:

    case IIC_XFRCNT:

        i2c->xfrcnt = value & 0x77;

        break;

    case 15:

    case IIC_XTCNTLSS:

        i2c->xtcntlss &= ~(value & 0xf0);

        if (value & IIC_XTCNTLSS_SRST) {

            /* Is it actually a full reset? U-Boot sets some regs before */

            ppc4xx_i2c_reset(DEVICE(i2c));

            break;

        }

        i2c->xtcntlss = value;

        break;

    case 16:

    case IIC_DIRECTCNTL:

        i2c->directcntl = value & (IIC_DIRECTCNTL_SDAC & IIC_DIRECTCNTL_SCLC);

        i2c->directcntl |= (value & IIC_DIRECTCNTL_SCLC ? 1 : 0);

        bitbang_i2c_set(i2c->bitbang, BITBANG_I2C_SCL,

include/hw/i2c/ppc4xx_i2c.h

+2 −1
Original line number Diff line number Diff line
@@ -46,7 +46,8 @@ typedef struct PPC4xxI2CState { 
    qemu_irq irq;

    MemoryRegion iomem;

    bitbang_i2c_interface *bitbang;

    uint8_t mdata;

    int mdidx;

    uint8_t mdata[4];

    uint8_t lmadr;

    uint8_t hmadr;

    uint8_t cntl;