Commit af13ae03 authored by Jia Liu's avatar Jia Liu Committed by Aurelien Jarno
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target-mips: Add ASE DSP processors 



Add 74kf and mips64dspr2-generic-cpu model for test.

Signed-off-by: default avatarJia Liu <proljc@gmail.com>
Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
parent b53371ed

target-mips/translate_init.c

+52 −0
Original line number Diff line number Diff line
@@ -311,6 +311,29 @@ static const mips_def_t mips_defs[] = 
        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,

        .mmu_type = MMU_TYPE_R4000,

    },

    {

        .name = "74Kf",

        .CP0_PRid = 0x00019700,

        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |

                    (MMU_TYPE_R4000 << CP0C0_MT),

        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |

                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |

                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |

                       (1 << CP0C1_CA),

        .CP0_Config2 = MIPS_CONFIG2,

        .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP),

        .CP0_LLAddr_rw_bitmask = 0,

        .CP0_LLAddr_shift = 4,

        .SYNCI_Step = 32,

        .CCRes = 2,

        .CP0_Status_rw_bitmask = 0x3778FF1F,

        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |

                    (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),

        .SEGBITS = 32,

        .PABITS = 32,

        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,

        .mmu_type = MMU_TYPE_R4000,

    },

#if defined(TARGET_MIPS64)

    {

        .name = "R4000",
@@ -484,6 +507,35 @@ static const mips_def_t mips_defs[] = 
      .insn_flags = CPU_LOONGSON2F,

      .mmu_type = MMU_TYPE_R4000,

    },

    {

        /* A generic CPU providing MIPS64 ASE DSP 2 features.

           FIXME: Eventually this should be replaced by a real CPU model. */

        .name = "mips64dspr2",

        .CP0_PRid = 0x00010000,

        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |

                       (MMU_TYPE_R4000 << CP0C0_MT),

        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |

                       (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |

                       (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |

                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),

        .CP0_Config2 = MIPS_CONFIG2,

        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),

        .CP0_LLAddr_rw_bitmask = 0,

        .CP0_LLAddr_shift = 0,

        .SYNCI_Step = 32,

        .CCRes = 2,

        .CP0_Status_rw_bitmask = 0x37FBFFFF,

        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |

                    (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |

                    (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),

        .SEGBITS = 42,

        /* The architectural limit is 59, but we have hardcoded 36 bit

           in some places...

        .PABITS = 59, */ /* the architectural limit */

        .PABITS = 36,

        .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,

        .mmu_type = MMU_TYPE_R4000,

    },



#endif

};