Commit ae7c5c85 authored by Peter Maydell's avatar Peter Maydell
Browse files

hw/intc/armv7m_nvic: Implement v8M CPPWR register 



The Coprocessor Power Control Register (CPPWR) is new in v8M.
It allows software to control whether coprocessors are allowed
to power down and lose their state. QEMU doesn't have any
notion of power control, so we choose the IMPDEF option of
making the whole register RAZ/WI (indicating that no coprocessors
can ever power down and lose state).

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180209165810.6668-5-peter.maydell@linaro.org
parent e8ab26c4

hw/intc/armv7m_nvic.c

+14 −0
Original line number Diff line number Diff line
@@ -776,6 +776,14 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) 
    switch (offset) {

    case 4: /* Interrupt Control Type.  */

        return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;

    case 0xc: /* CPPWR */

        if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {

            goto bad_offset;

        }

        /* We make the IMPDEF choice that nothing can ever go into a

         * non-retentive power state, which allows us to RAZ/WI this.

         */

        return 0;

    case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */

    {

        int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;
@@ -1175,6 +1183,12 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, 
    ARMCPU *cpu = s->cpu;



    switch (offset) {

    case 0xc: /* CPPWR */

        if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {

            goto bad_offset;

        }

        /* Make the IMPDEF choice to RAZ/WI this. */

        break;

    case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */

    {

        int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;