Commit ae52bd96 authored by Sebastian Macke's avatar Sebastian Macke Committed by Jia Liu
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target-openrisc: Correct wrong epcr register in interrupt handler 



This patch corrects several misbehaviors during an interrupt process.
Most of the time the pc is already correct and therefore no special treatment
of the exceptions is necessary.

Tested by checking crashing programs which otherwise work in or1ksim.

Signed-off-by: default avatarSebastian Macke <sebastian@macke.de>
Reviewed-by: default avatarJia Liu <proljc@gmail.com>
Signed-off-by: default avatarJia Liu <proljc@gmail.com>
parent 04359e6b

target-openrisc/interrupt.c

+7 −18
Original line number Diff line number Diff line
@@ -30,26 +30,15 @@ void openrisc_cpu_do_interrupt(CPUState *cs) 
    OpenRISCCPU *cpu = OPENRISC_CPU(cs);

    CPUOpenRISCState *env = &cpu->env;

#ifndef CONFIG_USER_ONLY

    if (env->flags & D_FLAG) { /* Delay Slot insn */



    env->epcr = env->pc;

    if (env->flags & D_FLAG) {

        env->flags &= ~D_FLAG;

        env->sr |= SR_DSX;

        if (env->exception_index == EXCP_TICK    ||

            env->exception_index == EXCP_INT     ||

            env->exception_index == EXCP_SYSCALL ||

            env->exception_index == EXCP_FPE) {

            env->epcr = env->jmp_pc;

        } else {

            env->epcr = env->pc - 4;

        }

    } else {

        if (env->exception_index == EXCP_TICK    ||

            env->exception_index == EXCP_INT     ||

            env->exception_index == EXCP_SYSCALL ||

            env->exception_index == EXCP_FPE) {

            env->epcr = env->npc;

        } else {

            env->epcr = env->pc;

        env->epcr -= 4;

    }

    if (env->exception_index == EXCP_SYSCALL) {

        env->epcr += 4;

    }



    /* For machine-state changed between user-mode and supervisor mode,