Commit ad601177 authored by Andreas Färber's avatar Andreas Färber
Browse files

alpha: Pass AlphaCPU array to Typhoon 



Also store it in TyphoonCchip.

Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
Acked-by: default avatarRichard Henderson <rth@twiddle.net>
parent 5f5e3350

hw/alpha_dp264.c

+9 −9
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ static void clipper_init(QEMUMachineInitArgs *args) 
    const char *kernel_filename = args->kernel_filename;

    const char *kernel_cmdline = args->kernel_cmdline;

    const char *initrd_filename = args->initrd_filename;

    CPUAlphaState *cpus[4];

    AlphaCPU *cpus[4];

    PCIBus *pci_bus;

    ISABus *isa_bus;

    qemu_irq rtc_irq;
@@ -62,12 +62,12 @@ static void clipper_init(QEMUMachineInitArgs *args) 
    /* Create up to 4 cpus.  */

    memset(cpus, 0, sizeof(cpus));

    for (i = 0; i < smp_cpus; ++i) {

        cpus[i] = cpu_init(cpu_model ? cpu_model : "ev67");

        cpus[i] = cpu_alpha_init(cpu_model ? cpu_model : "ev67");

    }



    cpus[0]->trap_arg0 = ram_size;

    cpus[0]->trap_arg1 = 0;

    cpus[0]->trap_arg2 = smp_cpus;

    cpus[0]->env.trap_arg0 = ram_size;

    cpus[0]->env.trap_arg1 = 0;

    cpus[0]->env.trap_arg2 = smp_cpus;



    /* Init the chipset.  */

    pci_bus = typhoon_init(ram_size, &isa_bus, &rtc_irq, cpus,
@@ -119,9 +119,9 @@ static void clipper_init(QEMUMachineInitArgs *args) 


    /* Start all cpus at the PALcode RESET entry point.  */

    for (i = 0; i < smp_cpus; ++i) {

        cpus[i]->pal_mode = 1;

        cpus[i]->pc = palcode_entry;

        cpus[i]->palbr = palcode_entry;

        cpus[i]->env.pal_mode = 1;

        cpus[i]->env.pc = palcode_entry;

        cpus[i]->env.palbr = palcode_entry;

    }



    /* Load a kernel.  */
@@ -136,7 +136,7 @@ static void clipper_init(QEMUMachineInitArgs *args) 
            exit(1);

        }



        cpus[0]->trap_arg1 = kernel_entry;

        cpus[0]->env.trap_arg1 = kernel_entry;



        param_offset = kernel_low - 0x6000;

hw/alpha_sys.h

+1 −1
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ 
#include "irq.h"





PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, CPUAlphaState *[4],

PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, AlphaCPU *[4],

                     pci_map_irq_fn);



/* alpha_pci.c.  */

hw/alpha_typhoon.c

+16 −13
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ typedef struct TyphoonCchip { 
    uint64_t drir;

    uint64_t dim[4];

    uint32_t iic[4];

    CPUAlphaState *cpu[4];

    AlphaCPU *cpu[4];

} TyphoonCchip;



typedef struct TyphoonWindow {
@@ -58,10 +58,11 @@ typedef struct TyphoonState { 
} TyphoonState;



/* Called when one of DRIR or DIM changes.  */

static void cpu_irq_change(CPUAlphaState *env, uint64_t req)

static void cpu_irq_change(AlphaCPU *cpu, uint64_t req)

{

    /* If there are any non-masked interrupts, tell the cpu.  */

    if (env) {

    if (cpu != NULL) {

        CPUAlphaState *env = &cpu->env;

        if (req) {

            cpu_interrupt(env, CPU_INTERRUPT_HARD);

        } else {
@@ -353,8 +354,9 @@ static void cchip_write(void *opaque, hwaddr addr, 
        if ((newval ^ oldval) & 0xff0) {

            int i;

            for (i = 0; i < 4; ++i) {

                CPUAlphaState *env = s->cchip.cpu[i];

                if (env) {

                AlphaCPU *cpu = s->cchip.cpu[i];

                if (cpu != NULL) {

                    CPUAlphaState *env = &cpu->env;

                    /* IPI can be either cleared or set by the write.  */

                    if (newval & (1 << (i + 8))) {

                        cpu_interrupt(env, CPU_INTERRUPT_SMP);
@@ -661,8 +663,8 @@ static void typhoon_set_timer_irq(void *opaque, int irq, int level) 


    /* Deliver the interrupt to each CPU, considering each CPU's IIC.  */

    for (i = 0; i < 4; ++i) {

        CPUAlphaState *env = s->cchip.cpu[i];

        if (env) {

        AlphaCPU *cpu = s->cchip.cpu[i];

        if (cpu != NULL) {

            uint32_t iic = s->cchip.iic[i];



            /* ??? The verbage in Section 10.2.2.10 isn't 100% clear.
@@ -681,7 +683,7 @@ static void typhoon_set_timer_irq(void *opaque, int irq, int level) 
                /* Set the ITI bit for this cpu.  */

                s->cchip.misc |= 1 << (i + 4);

                /* And signal the interrupt.  */

                cpu_interrupt(env, CPU_INTERRUPT_TIMER);

                cpu_interrupt(&cpu->env, CPU_INTERRUPT_TIMER);

            }

        }

    }
@@ -694,12 +696,12 @@ static void typhoon_alarm_timer(void *opaque) 


    /* Set the ITI bit for this cpu.  */

    s->cchip.misc |= 1 << (cpu + 4);

    cpu_interrupt(s->cchip.cpu[cpu], CPU_INTERRUPT_TIMER);

    cpu_interrupt(&s->cchip.cpu[cpu]->env, CPU_INTERRUPT_TIMER);

}



PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,

                     qemu_irq *p_rtc_irq,

                     CPUAlphaState *cpus[4], pci_map_irq_fn sys_map_irq)

                     AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq)

{

    const uint64_t MB = 1024 * 1024;

    const uint64_t GB = 1024 * MB;
@@ -719,9 +721,10 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, 


    /* Remember the CPUs so that we can deliver interrupts to them.  */

    for (i = 0; i < 4; i++) {

        CPUAlphaState *env = cpus[i];

        s->cchip.cpu[i] = env;

        if (env) {

        AlphaCPU *cpu = cpus[i];

        s->cchip.cpu[i] = cpu;

        if (cpu != NULL) {

            CPUAlphaState *env = &cpu->env;

            env->alarm_timer = qemu_new_timer_ns(rtc_clock,

                                                 typhoon_alarm_timer,

                                                 (void *)((uintptr_t)s + i));