Commit ad600a4d authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/rth/tags/tcg-next-20140422' into staging 



Pull tcg 2014-04-22

# gpg: Signature made Tue 22 Apr 2014 22:00:04 BST using RSA key ID 4DD0279B
# gpg: Can't check signature: public key not found

* remotes/rth/tags/tcg-next-20140422:
  tcg: Use HOST_WORDS_BIGENDIAN
  tcg: Fix fallback from muls2_i64 to mulu2_i64
  tcg: Use tcg_gen_mulu2_i32 in tcg_gen_muls2_i32
  tcg: Relax requirement for mulu2_i32 on 32-bit hosts
  tcg-s390: Remove W constraint
  tcg-sparc: Use the type parameter to tcg_target_const_match
  tcg-ppc64: Use the type parameter to tcg_target_const_match
  tcg-aarch64: Remove w constraint
  tcg: Add TCGType parameter to tcg_target_const_match
  tcg: Fix out of range shift in deposit optimizations
  tci: Mask shift counts to avoid undefined behavior
  tcg: Mask shift quantities while folding
  tcg: Use "unspecified behavior" for shifts
  tcg: Fix warning (1 bit signed bitfield entry) and replace int by bool

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents ba3627ec 02eb19d0

tcg/README

+13 −5
Original line number Diff line number Diff line
@@ -36,6 +36,12 @@ or a memory location which is stored in a register outside QEMU TBs 
A TCG "basic block" corresponds to a list of instructions terminated

by a branch instruction. 



An operation with "undefined behavior" may result in a crash.



An operation with "unspecified behavior" shall not crash.  However,

the result may be one of several possibilities so may be considered

an "undefined result".



3) Intermediate representation



3.1) Introduction
@@ -239,23 +245,25 @@ t0=t1|~t2 


* shl_i32/i64 t0, t1, t2



t0=t1 << t2. Undefined behavior if t2 < 0 or t2 >= 32 (resp 64)

t0=t1 << t2. Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)



* shr_i32/i64 t0, t1, t2



t0=t1 >> t2 (unsigned). Undefined behavior if t2 < 0 or t2 >= 32 (resp 64)

t0=t1 >> t2 (unsigned). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)



* sar_i32/i64 t0, t1, t2



t0=t1 >> t2 (signed). Undefined behavior if t2 < 0 or t2 >= 32 (resp 64)

t0=t1 >> t2 (signed). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)



* rotl_i32/i64 t0, t1, t2



Rotation of t2 bits to the left. Undefined behavior if t2 < 0 or t2 >= 32 (resp 64)

Rotation of t2 bits to the left.

Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)



* rotr_i32/i64 t0, t1, t2



Rotation of t2 bits to the right. Undefined behavior if t2 < 0 or t2 >= 32 (resp 64)

Rotation of t2 bits to the right.

Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)



********* Misc

tcg/aarch64/tcg-target.c

+22 −26
Original line number Diff line number Diff line
@@ -102,11 +102,10 @@ static inline void patch_reloc(uint8_t *code_ptr, int type, 
    }

}



#define TCG_CT_CONST_IS32 0x100

#define TCG_CT_CONST_AIMM 0x200

#define TCG_CT_CONST_LIMM 0x400

#define TCG_CT_CONST_ZERO 0x800

#define TCG_CT_CONST_MONE 0x1000

#define TCG_CT_CONST_AIMM 0x100

#define TCG_CT_CONST_LIMM 0x200

#define TCG_CT_CONST_ZERO 0x400

#define TCG_CT_CONST_MONE 0x800



/* parse target specific constraints */

static int target_parse_constraint(TCGArgConstraint *ct,
@@ -131,9 +130,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, 
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3);

#endif

        break;

    case 'w': /* The operand should be considered 32-bit.  */

        ct->ct |= TCG_CT_CONST_IS32;

        break;

    case 'A': /* Valid for arithmetic immediate (positive or negative).  */

        ct->ct |= TCG_CT_CONST_AIMM;

        break;
@@ -180,7 +176,7 @@ static inline bool is_limm(uint64_t val) 
    return (val & (val - 1)) == 0;

}



static int tcg_target_const_match(tcg_target_long val,

static int tcg_target_const_match(tcg_target_long val, TCGType type,

                                  const TCGArgConstraint *arg_ct)

{

    int ct = arg_ct->ct;
@@ -188,7 +184,7 @@ static int tcg_target_const_match(tcg_target_long val, 
    if (ct & TCG_CT_CONST) {

        return 1;

    }

    if (ct & TCG_CT_CONST_IS32) {

    if (type == TCG_TYPE_I32) {

        val = (int32_t)val;

    }

    if ((ct & TCG_CT_CONST_AIMM) && (is_aimm(val) || is_aimm(-val))) {
@@ -1053,7 +1049,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 
    tcg_out_goto(s, (intptr_t)lb->raddr);

}



static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOp opc,

static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOp opc,

                                TCGReg data_reg, TCGReg addr_reg,

                                int mem_index,

                                uint8_t *raddr, uint8_t *label_ptr)
@@ -1226,7 +1222,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 


    tcg_out_tlb_read(s, addr_reg, s_bits, &label_ptr, mem_index, 1);

    tcg_out_qemu_ld_direct(s, memop, data_reg, addr_reg, TCG_REG_X1);

    add_qemu_ldst_label(s, 1, memop, data_reg, addr_reg,

    add_qemu_ldst_label(s, true, memop, data_reg, addr_reg,

                        mem_index, s->code_ptr, label_ptr);

#else /* !CONFIG_SOFTMMU */

    tcg_out_qemu_ld_direct(s, memop, data_reg, addr_reg,
@@ -1243,7 +1239,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 


    tcg_out_tlb_read(s, addr_reg, s_bits, &label_ptr, mem_index, 0);

    tcg_out_qemu_st_direct(s, memop, data_reg, addr_reg, TCG_REG_X1);

    add_qemu_ldst_label(s, 0, memop, data_reg, addr_reg,

    add_qemu_ldst_label(s, false, memop, data_reg, addr_reg,

                        mem_index, s->code_ptr, label_ptr);

#else /* !CONFIG_SOFTMMU */

    tcg_out_qemu_st_direct(s, memop, data_reg, addr_reg,
@@ -1663,9 +1659,9 @@ static const TCGTargetOpDef aarch64_op_defs[] = { 
    { INDEX_op_st32_i64, { "rZ", "r" } },

    { INDEX_op_st_i64, { "rZ", "r" } },



    { INDEX_op_add_i32, { "r", "r", "rwA" } },

    { INDEX_op_add_i32, { "r", "r", "rA" } },

    { INDEX_op_add_i64, { "r", "r", "rA" } },

    { INDEX_op_sub_i32, { "r", "r", "rwA" } },

    { INDEX_op_sub_i32, { "r", "r", "rA" } },

    { INDEX_op_sub_i64, { "r", "r", "rA" } },

    { INDEX_op_mul_i32, { "r", "r", "r" } },

    { INDEX_op_mul_i64, { "r", "r", "r" } },
@@ -1677,17 +1673,17 @@ static const TCGTargetOpDef aarch64_op_defs[] = { 
    { INDEX_op_rem_i64, { "r", "r", "r" } },

    { INDEX_op_remu_i32, { "r", "r", "r" } },

    { INDEX_op_remu_i64, { "r", "r", "r" } },

    { INDEX_op_and_i32, { "r", "r", "rwL" } },

    { INDEX_op_and_i32, { "r", "r", "rL" } },

    { INDEX_op_and_i64, { "r", "r", "rL" } },

    { INDEX_op_or_i32, { "r", "r", "rwL" } },

    { INDEX_op_or_i32, { "r", "r", "rL" } },

    { INDEX_op_or_i64, { "r", "r", "rL" } },

    { INDEX_op_xor_i32, { "r", "r", "rwL" } },

    { INDEX_op_xor_i32, { "r", "r", "rL" } },

    { INDEX_op_xor_i64, { "r", "r", "rL" } },

    { INDEX_op_andc_i32, { "r", "r", "rwL" } },

    { INDEX_op_andc_i32, { "r", "r", "rL" } },

    { INDEX_op_andc_i64, { "r", "r", "rL" } },

    { INDEX_op_orc_i32, { "r", "r", "rwL" } },

    { INDEX_op_orc_i32, { "r", "r", "rL" } },

    { INDEX_op_orc_i64, { "r", "r", "rL" } },

    { INDEX_op_eqv_i32, { "r", "r", "rwL" } },

    { INDEX_op_eqv_i32, { "r", "r", "rL" } },

    { INDEX_op_eqv_i64, { "r", "r", "rL" } },



    { INDEX_op_neg_i32, { "r", "r" } },
@@ -1706,11 +1702,11 @@ static const TCGTargetOpDef aarch64_op_defs[] = { 
    { INDEX_op_rotl_i64, { "r", "r", "ri" } },

    { INDEX_op_rotr_i64, { "r", "r", "ri" } },



    { INDEX_op_brcond_i32, { "r", "rwA" } },

    { INDEX_op_brcond_i32, { "r", "rA" } },

    { INDEX_op_brcond_i64, { "r", "rA" } },

    { INDEX_op_setcond_i32, { "r", "r", "rwA" } },

    { INDEX_op_setcond_i32, { "r", "r", "rA" } },

    { INDEX_op_setcond_i64, { "r", "r", "rA" } },

    { INDEX_op_movcond_i32, { "r", "r", "rwA", "rZ", "rZ" } },

    { INDEX_op_movcond_i32, { "r", "r", "rA", "rZ", "rZ" } },

    { INDEX_op_movcond_i64, { "r", "r", "rA", "rZ", "rZ" } },



    { INDEX_op_qemu_ld_i32, { "r", "l" } },
@@ -1739,9 +1735,9 @@ static const TCGTargetOpDef aarch64_op_defs[] = { 
    { INDEX_op_deposit_i32, { "r", "0", "rZ" } },

    { INDEX_op_deposit_i64, { "r", "0", "rZ" } },



    { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rwA", "rwMZ" } },

    { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },

    { INDEX_op_add2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },

    { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rwA", "rwMZ" } },

    { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },

    { INDEX_op_sub2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },



    { INDEX_op_muluh_i64, { "r", "r", "r" } },

tcg/aarch64/tcg-target.h

+0 −1
Original line number Diff line number Diff line
@@ -13,7 +13,6 @@ 
#ifndef TCG_TARGET_AARCH64

#define TCG_TARGET_AARCH64 1



#undef TCG_TARGET_WORDS_BIGENDIAN

#undef TCG_TARGET_STACK_GROWSUP



typedef enum {

tcg/arm/tcg-target.c

+4 −4
Original line number Diff line number Diff line
@@ -261,7 +261,7 @@ static inline int check_fit_imm(uint32_t imm) 
 * mov operand2:     values represented with x << (2 * y), x < 0x100

 * add, sub, eor...: ditto

 */

static inline int tcg_target_const_match(tcg_target_long val,

static inline int tcg_target_const_match(tcg_target_long val, TCGType type,

                                         const TCGArgConstraint *arg_ct)

{

    int ct;
@@ -1253,7 +1253,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, 
/* Record the context of a call to the out of line helper code for the slow

   path for a load or store, so that we can later generate the correct

   helper code.  */

static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOp opc,

static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOp opc,

                                TCGReg datalo, TCGReg datahi, TCGReg addrlo,

                                TCGReg addrhi, int mem_index,

                                uint8_t *raddr, uint8_t *label_ptr)
@@ -1519,7 +1519,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) 


    tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend);



    add_qemu_ldst_label(s, 1, opc, datalo, datahi, addrlo, addrhi,

    add_qemu_ldst_label(s, true, opc, datalo, datahi, addrlo, addrhi,

                        mem_index, s->code_ptr, label_ptr);

#else /* !CONFIG_SOFTMMU */

    if (GUEST_BASE) {
@@ -1647,7 +1647,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) 
    label_ptr = s->code_ptr;

    tcg_out_bl_noaddr(s, COND_NE);



    add_qemu_ldst_label(s, 0, opc, datalo, datahi, addrlo, addrhi,

    add_qemu_ldst_label(s, false, opc, datalo, datahi, addrlo, addrhi,

                        mem_index, s->code_ptr, label_ptr);

#else /* !CONFIG_SOFTMMU */

    if (GUEST_BASE) {

tcg/arm/tcg-target.h

+1 −1
Original line number Diff line number Diff line
@@ -25,7 +25,6 @@ 
#ifndef TCG_TARGET_ARM 

#define TCG_TARGET_ARM 1



#undef TCG_TARGET_WORDS_BIGENDIAN

#undef TCG_TARGET_STACK_GROWSUP



typedef enum {
@@ -79,6 +78,7 @@ extern bool use_idiv_instructions; 
#define TCG_TARGET_HAS_nor_i32          0

#define TCG_TARGET_HAS_deposit_i32      1

#define TCG_TARGET_HAS_movcond_i32      1

#define TCG_TARGET_HAS_mulu2_i32        1

#define TCG_TARGET_HAS_muls2_i32        1

#define TCG_TARGET_HAS_muluh_i32        0

#define TCG_TARGET_HAS_mulsh_i32        0