Commit ac689a2e authored by Aaron Lindsay's avatar Aaron Lindsay Committed by Peter Maydell
Browse files

target/arm: PMU: Set PMCR.N to 4 



This both advertises that we support four counters and enables them
because the pmu_num_counters() reads this value from PMCR.

Signed-off-by: default avatarAaron Lindsay <alindsay@codeaurora.org>
Signed-off-by: default avatarAaron Lindsay <aaron@os.amperecomputing.com>
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Message-id: 20181211151945.29137-13-aaron@os.amperecomputing.com
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent b2e23725

target/arm/helper.c

+5 −5
Original line number Diff line number Diff line
@@ -1777,7 +1777,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { 
      .access = PL1_W, .type = ARM_CP_NOP },

    /* Performance monitors are implementation defined in v7,

     * but with an ARM recommended set of registers, which we

     * follow (although we don't actually implement any counters)

     * follow.

     *

     * Performance registers fall into three categories:

     *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
@@ -5671,10 +5671,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) 
    }

    if (arm_feature(env, ARM_FEATURE_V7)) {

        /* v7 performance monitor control register: same implementor

         * field as main ID register, and we implement only the cycle

         * count register.

         * field as main ID register, and we implement four counters in

         * addition to the cycle count register.

         */

        unsigned int i, pmcrn = 0;

        unsigned int i, pmcrn = 4;

        ARMCPRegInfo pmcr = {

            .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,

            .access = PL0_RW,
@@ -5689,7 +5689,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) 
            .access = PL0_RW, .accessfn = pmreg_access,

            .type = ARM_CP_IO,

            .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),

            .resetvalue = cpu->midr & 0xff000000,

            .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT),

            .writefn = pmcr_write, .raw_writefn = raw_write,

        };

        define_one_arm_cp_reg(cpu, &pmcr);