Commit ac2e8522 authored by Aurelien Jarno's avatar Aurelien Jarno
Browse files

sh4: sh_pci. Register resouces both at A7 and P4. 



Add resource registration both for P4 and A7.
This is needed because of #5935 SH4: Eliminate P4 to A7 mangling.
Additionally, {reg,iop,mem}base which is no longer used are removed.

Signed-off-by: default avatarTakashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6433 c046a42c-6fe2-441c-8c8c-71466251a162
parent d2c639d6

hw/sh_pci.c

+7 −10
Original line number Diff line number Diff line
@@ -29,9 +29,6 @@ 
typedef struct {

    PCIBus *bus;

    PCIDevice *dev;

    uint32_t regbase;

    uint32_t iopbase;

    uint32_t membase;

    uint32_t par;

    uint32_t mbr;

    uint32_t iobr;
@@ -181,15 +178,15 @@ PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 


    p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),

                                 -1, NULL, NULL);

    p->regbase = 0x1e200000;

    p->iopbase = 0x1e240000;

    p->membase = 0xfd000000;

    reg = cpu_register_io_memory(0, sh_pci_reg.r, sh_pci_reg.w, p);

    mem = cpu_register_io_memory(0, sh_pci_mem.r, sh_pci_mem.w, p);

    iop = cpu_register_io_memory(0, sh_pci_iop.r, sh_pci_iop.w, p);

    cpu_register_physical_memory(p->regbase, 0x224, reg);

    cpu_register_physical_memory(p->iopbase, 0x40000, iop);

    cpu_register_physical_memory(p->membase, 0x1000000, mem);

    mem = cpu_register_io_memory(0, sh_pci_mem.r, sh_pci_mem.w, p);

    cpu_register_physical_memory(0x1e200000, 0x224, reg);

    cpu_register_physical_memory(0x1e240000, 0x40000, iop);

    cpu_register_physical_memory(0x1d000000, 0x1000000, mem);

    cpu_register_physical_memory(0xfe200000, 0x224, reg);

    cpu_register_physical_memory(0xfe240000, 0x40000, iop);

    cpu_register_physical_memory(0xfd000000, 0x1000000, mem);



    p->dev->config[0x00] = 0x54; // HITACHI

    p->dev->config[0x01] = 0x10; //