Loading hw/net/opencores_eth.c +16 −17 Original line number Diff line number Diff line Loading @@ -33,6 +33,7 @@ #include "qemu/osdep.h" #include "hw/hw.h" #include "hw/net/mii.h" #include "hw/sysbus.h" #include "net/net.h" #include "sysemu/sysemu.h" Loading @@ -55,12 +56,6 @@ /* PHY MII registers */ enum { MII_BMCR, MII_BMSR, MII_PHYIDR1, MII_PHYIDR2, MII_ANAR, MII_ANLPAR, MII_REG_MAX = 16, }; Loading @@ -72,10 +67,11 @@ typedef struct Mii { static void mii_set_link(Mii *s, bool link_ok) { if (link_ok) { s->regs[MII_BMSR] |= 0x4; s->regs[MII_ANLPAR] |= 0x01e1; s->regs[MII_BMSR] |= MII_BMSR_LINK_ST; s->regs[MII_ANLPAR] |= MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD | MII_ANLPAR_10 | MII_ANLPAR_CSMACD; } else { s->regs[MII_BMSR] &= ~0x4; s->regs[MII_BMSR] &= ~MII_BMSR_LINK_ST; s->regs[MII_ANLPAR] &= 0x01ff; } s->link_ok = link_ok; Loading @@ -84,11 +80,14 @@ static void mii_set_link(Mii *s, bool link_ok) static void mii_reset(Mii *s) { memset(s->regs, 0, sizeof(s->regs)); s->regs[MII_BMCR] = 0x1000; s->regs[MII_BMSR] = 0x7868; /* no ext regs */ s->regs[MII_PHYIDR1] = 0x2000; s->regs[MII_PHYIDR2] = 0x5c90; s->regs[MII_ANAR] = 0x01e1; s->regs[MII_BMCR] = MII_BMCR_AUTOEN; s->regs[MII_BMSR] = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD | MII_BMSR_10T_HD | MII_BMSR_MFPS | MII_BMSR_AN_COMP | MII_BMSR_AUTONEG; s->regs[MII_PHYID1] = 0x2000; s->regs[MII_PHYID2] = 0x5c90; s->regs[MII_ANAR] = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 | MII_ANAR_CSMACD; mii_set_link(s, s->link_ok); } Loading @@ -98,7 +97,7 @@ static void mii_ro(Mii *s, uint16_t v) static void mii_write_bmcr(Mii *s, uint16_t v) { if (v & 0x8000) { if (v & MII_BMCR_RESET) { mii_reset(s); } else { s->regs[MII_BMCR] = v; Loading @@ -110,8 +109,8 @@ static void mii_write_host(Mii *s, unsigned idx, uint16_t v) static void (*reg_write[MII_REG_MAX])(Mii *s, uint16_t v) = { [MII_BMCR] = mii_write_bmcr, [MII_BMSR] = mii_ro, [MII_PHYIDR1] = mii_ro, [MII_PHYIDR2] = mii_ro, [MII_PHYID1] = mii_ro, [MII_PHYID2] = mii_ro, }; if (idx < MII_REG_MAX) { Loading Loading
hw/net/opencores_eth.c +16 −17 Original line number Diff line number Diff line Loading @@ -33,6 +33,7 @@ #include "qemu/osdep.h" #include "hw/hw.h" #include "hw/net/mii.h" #include "hw/sysbus.h" #include "net/net.h" #include "sysemu/sysemu.h" Loading @@ -55,12 +56,6 @@ /* PHY MII registers */ enum { MII_BMCR, MII_BMSR, MII_PHYIDR1, MII_PHYIDR2, MII_ANAR, MII_ANLPAR, MII_REG_MAX = 16, }; Loading @@ -72,10 +67,11 @@ typedef struct Mii { static void mii_set_link(Mii *s, bool link_ok) { if (link_ok) { s->regs[MII_BMSR] |= 0x4; s->regs[MII_ANLPAR] |= 0x01e1; s->regs[MII_BMSR] |= MII_BMSR_LINK_ST; s->regs[MII_ANLPAR] |= MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD | MII_ANLPAR_10 | MII_ANLPAR_CSMACD; } else { s->regs[MII_BMSR] &= ~0x4; s->regs[MII_BMSR] &= ~MII_BMSR_LINK_ST; s->regs[MII_ANLPAR] &= 0x01ff; } s->link_ok = link_ok; Loading @@ -84,11 +80,14 @@ static void mii_set_link(Mii *s, bool link_ok) static void mii_reset(Mii *s) { memset(s->regs, 0, sizeof(s->regs)); s->regs[MII_BMCR] = 0x1000; s->regs[MII_BMSR] = 0x7868; /* no ext regs */ s->regs[MII_PHYIDR1] = 0x2000; s->regs[MII_PHYIDR2] = 0x5c90; s->regs[MII_ANAR] = 0x01e1; s->regs[MII_BMCR] = MII_BMCR_AUTOEN; s->regs[MII_BMSR] = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD | MII_BMSR_10T_HD | MII_BMSR_MFPS | MII_BMSR_AN_COMP | MII_BMSR_AUTONEG; s->regs[MII_PHYID1] = 0x2000; s->regs[MII_PHYID2] = 0x5c90; s->regs[MII_ANAR] = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 | MII_ANAR_CSMACD; mii_set_link(s, s->link_ok); } Loading @@ -98,7 +97,7 @@ static void mii_ro(Mii *s, uint16_t v) static void mii_write_bmcr(Mii *s, uint16_t v) { if (v & 0x8000) { if (v & MII_BMCR_RESET) { mii_reset(s); } else { s->regs[MII_BMCR] = v; Loading @@ -110,8 +109,8 @@ static void mii_write_host(Mii *s, unsigned idx, uint16_t v) static void (*reg_write[MII_REG_MAX])(Mii *s, uint16_t v) = { [MII_BMCR] = mii_write_bmcr, [MII_BMSR] = mii_ro, [MII_PHYIDR1] = mii_ro, [MII_PHYIDR2] = mii_ro, [MII_PHYID1] = mii_ro, [MII_PHYID2] = mii_ro, }; if (idx < MII_REG_MAX) { Loading