Commit aa4bb587 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by David Gibson
Browse files

ppc: Add mmu_model defines for arch 2.03 and 2.07 



This removes unused POWERPC_MMU_2_06a/POWERPC_MMU_2_06d.

This replaces POWERPC_MMU_64B with POWERPC_MMU_2_03 for POWER5+ to be
more explicit about the version of the PowerISA supported.

This defines POWERPC_MMU_2_07 and uses it for the POWER8 CPU family.
This will not have an immediate effect now but it will in the following
patch.

This should cause no behavioural change.

Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
[aik: rebased, changed commit log]
Signed-off-by: default avatarAlexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent a23dec10

target-ppc/cpu.h

+5 −5
Original line number Diff line number Diff line
@@ -117,14 +117,14 @@ enum powerpc_mmu_t { 
#define POWERPC_MMU_AMR      0x00040000

    /* 64 bits PowerPC MMU                                     */

    POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,

    /* Architecture 2.03 and later (has LPCR) */

    POWERPC_MMU_2_03       = POWERPC_MMU_64 | 0x00000002,

    /* Architecture 2.06 variant                               */

    POWERPC_MMU_2_06       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG

                             | POWERPC_MMU_AMR | 0x00000003,

    /* Architecture 2.06 "degraded" (no 1T segments)           */

    POWERPC_MMU_2_06a      = POWERPC_MMU_64 | POWERPC_MMU_AMR

                             | 0x00000003,

    /* Architecture 2.06 "degraded" (no 1T segments or AMR)    */

    POWERPC_MMU_2_06d      = POWERPC_MMU_64 | 0x00000003,

    /* Architecture 2.07 variant                               */

    POWERPC_MMU_2_07       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG

                             | POWERPC_MMU_AMR | 0x00000004,

#endif /* defined(TARGET_PPC64) */

};

target-ppc/kvm.c

+5 −3
Original line number Diff line number Diff line
@@ -259,7 +259,8 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, 
            info->flags |= KVM_PPC_1T_SEGMENTS;

        }



        if (env->mmu_model == POWERPC_MMU_2_06) {

        if (env->mmu_model == POWERPC_MMU_2_06 ||

            env->mmu_model == POWERPC_MMU_2_07) {

            info->slb_size = 32;

        } else {

            info->slb_size = 64;
@@ -272,8 +273,9 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, 
        info->sps[i].enc[0].pte_enc = 0;

        i++;



        /* 64K on MMU 2.06 */

        if (env->mmu_model == POWERPC_MMU_2_06) {

        /* 64K on MMU 2.06 and later */

        if (env->mmu_model == POWERPC_MMU_2_06 ||

            env->mmu_model == POWERPC_MMU_2_07) {

            info->sps[i].page_shift = 16;

            info->sps[i].slb_enc = 0x110;

            info->sps[i].enc[0].page_shift = 16;

target-ppc/mmu_helper.c

+8 −8
Original line number Diff line number Diff line
@@ -1293,9 +1293,9 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) 
        break;

#if defined(TARGET_PPC64)

    case POWERPC_MMU_64B:

    case POWERPC_MMU_2_03:

    case POWERPC_MMU_2_06:

    case POWERPC_MMU_2_06a:

    case POWERPC_MMU_2_06d:

    case POWERPC_MMU_2_07:

        dump_slb(f, cpu_fprintf, env);

        break;

#endif
@@ -1433,9 +1433,9 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 
    switch (env->mmu_model) {

#if defined(TARGET_PPC64)

    case POWERPC_MMU_64B:

    case POWERPC_MMU_2_03:

    case POWERPC_MMU_2_06:

    case POWERPC_MMU_2_06a:

    case POWERPC_MMU_2_06d:

    case POWERPC_MMU_2_07:

        return ppc_hash64_get_phys_page_debug(env, addr);

#endif
@@ -1937,9 +1937,9 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) 
    case POWERPC_MMU_601:

#if defined(TARGET_PPC64)

    case POWERPC_MMU_64B:

    case POWERPC_MMU_2_03:

    case POWERPC_MMU_2_06:

    case POWERPC_MMU_2_06a:

    case POWERPC_MMU_2_06d:

    case POWERPC_MMU_2_07:

#endif /* defined(TARGET_PPC64) */

        tlb_flush(CPU(cpu), 1);

        break;
@@ -2011,9 +2011,9 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) 
        break;

#if defined(TARGET_PPC64)

    case POWERPC_MMU_64B:

    case POWERPC_MMU_2_03:

    case POWERPC_MMU_2_06:

    case POWERPC_MMU_2_06a:

    case POWERPC_MMU_2_06d:

    case POWERPC_MMU_2_07:

        /* tlbie invalidate TLBs for all segments */

        /* XXX: given the fact that there are too many segments to invalidate,

         *      and we still don't have a tlb_flush_mask(env, n, mask) in QEMU,

target-ppc/translate.c

+2 −2
Original line number Diff line number Diff line
@@ -11327,9 +11327,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 
    case POWERPC_MMU_SOFT_74xx:

#if defined(TARGET_PPC64)

    case POWERPC_MMU_64B:

    case POWERPC_MMU_2_03:

    case POWERPC_MMU_2_06:

    case POWERPC_MMU_2_06a:

    case POWERPC_MMU_2_06d:

    case POWERPC_MMU_2_07:

#endif

        cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "   DAR " TARGET_FMT_lx

                       "  DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],

target-ppc/translate_init.c

+2 −2
Original line number Diff line number Diff line
@@ -8019,7 +8019,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 
                    (1ull << MSR_DR) |

                    (1ull << MSR_PMM) |

                    (1ull << MSR_RI);

    pcc->mmu_model = POWERPC_MMU_64B;

    pcc->mmu_model = POWERPC_MMU_2_03;

#if defined(CONFIG_SOFTMMU)

    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;

#endif
@@ -8243,7 +8243,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 
                    (1ull << MSR_PMM) |

                    (1ull << MSR_RI) |

                    (1ull << MSR_LE);

    pcc->mmu_model = POWERPC_MMU_2_06;

    pcc->mmu_model = POWERPC_MMU_2_07;

#if defined(CONFIG_SOFTMMU)

    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;

#endif