Commit a8f1b43c authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/rth/tags/tcg-pull-20150313' into staging 



Pool TCG data, and ALWAYS/NEVER fix

# gpg: Signature made Fri Mar 13 20:09:09 2015 GMT using RSA key ID 4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg:                 aka "Richard Henderson <rth@redhat.com>"
# gpg:                 aka "Richard Henderson <rth@twiddle.net>"

* remotes/rth/tags/tcg-pull-20150313:
  tcg: Complete handling of ALWAYS and NEVER
  tcg: Use tcg_malloc to allocate TCGLabel
  tcg: Change generator-side labels to a pointer
  tcg: Change translator-side labels to a pointer
  tcg-ia64: Use tcg_malloc to allocate TCGLabelQemuLdst
  tcg: Use tcg_malloc to allocate TCGLabelQemuLdst

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 7ccfb495 37ed3bf1

include/exec/gen-icount.h

+2 −2
Original line number Diff line number Diff line
@@ -6,8 +6,8 @@ 
/* Helpers for instruction counting code generation.  */



static TCGArg *icount_arg;

static int icount_label;

static int exitreq_label;

static TCGLabel *icount_label;

static TCGLabel *exitreq_label;



static inline void gen_tb_start(TranslationBlock *tb)

{

target-alpha/translate.c

+2 −2
Original line number Diff line number Diff line
@@ -388,7 +388,7 @@ static ExitStatus gen_store_conditional(DisasContext *ctx, int ra, int rb, 
    /* ??? In system mode we are never multi-threaded, so CAS can be

       implemented via a non-atomic load-compare-store sequence.  */

    {

        int lab_fail, lab_done;

        TCGLabel *lab_fail, *lab_done;

        TCGv val;



        lab_fail = gen_new_label();
@@ -465,7 +465,7 @@ static ExitStatus gen_bcond_internal(DisasContext *ctx, TCGCond cond, 
                                     TCGv cmp, int32_t disp)

{

    uint64_t dest = ctx->pc + (disp << 2);

    int lab_true = gen_new_label();

    TCGLabel *lab_true = gen_new_label();



    if (use_goto_tb(ctx, dest)) {

        tcg_gen_brcondi_i64(cond, cmp, 0, lab_true);

target-arm/translate-a64.c

+13 −13
Original line number Diff line number Diff line
@@ -1096,7 +1096,7 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn) 
{

    unsigned int sf, op, rt;

    uint64_t addr;

    int label_match;

    TCGLabel *label_match;

    TCGv_i64 tcg_cmp;



    sf = extract32(insn, 31, 1);
@@ -1125,7 +1125,7 @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn) 
{

    unsigned int bit_pos, op, rt;

    uint64_t addr;

    int label_match;

    TCGLabel *label_match;

    TCGv_i64 tcg_cmp;



    bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
@@ -1164,7 +1164,7 @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn) 


    if (cond < 0x0e) {

        /* genuinely conditional branches */

        int label_match = gen_new_label();

        TCGLabel *label_match = gen_new_label();

        arm_gen_test_cc(cond, label_match);

        gen_goto_tb(s, 0, s->pc);

        gen_set_label(label_match);
@@ -1711,8 +1711,8 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, 
     * }

     * env->exclusive_addr = -1;

     */

    int fail_label = gen_new_label();

    int done_label = gen_new_label();

    TCGLabel *fail_label = gen_new_label();

    TCGLabel *done_label = gen_new_label();

    TCGv_i64 addr = tcg_temp_local_new_i64();

    TCGv_i64 tmp;
@@ -3537,7 +3537,7 @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn) 
static void disas_cc(DisasContext *s, uint32_t insn)

{

    unsigned int sf, op, y, cond, rn, nzcv, is_imm;

    int label_continue = -1;

    TCGLabel *label_continue = NULL;

    TCGv_i64 tcg_tmp, tcg_y, tcg_rn;



    if (!extract32(insn, 29, 1)) {
@@ -3557,7 +3557,7 @@ static void disas_cc(DisasContext *s, uint32_t insn) 
    nzcv = extract32(insn, 0, 4);



    if (cond < 0x0e) { /* not always */

        int label_match = gen_new_label();

        TCGLabel *label_match = gen_new_label();

        label_continue = gen_new_label();

        arm_gen_test_cc(cond, label_match);

        /* nomatch: */
@@ -3630,8 +3630,8 @@ static void disas_cond_select(DisasContext *s, uint32_t insn) 
        /* OPTME: we could use movcond here, at the cost of duplicating

         * a lot of the arm_gen_test_cc() logic.

         */

        int label_match = gen_new_label();

        int label_continue = gen_new_label();

        TCGLabel *label_match = gen_new_label();

        TCGLabel *label_continue = gen_new_label();



        arm_gen_test_cc(cond, label_match);

        /* nomatch: */
@@ -4104,7 +4104,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn) 
{

    unsigned int mos, type, rm, cond, rn, op, nzcv;

    TCGv_i64 tcg_flags;

    int label_continue = -1;

    TCGLabel *label_continue = NULL;



    mos = extract32(insn, 29, 3);

    type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
@@ -4124,7 +4124,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn) 
    }



    if (cond < 0x0e) { /* not always */

        int label_match = gen_new_label();

        TCGLabel *label_match = gen_new_label();

        label_continue = gen_new_label();

        arm_gen_test_cc(cond, label_match);

        /* nomatch: */
@@ -4165,7 +4165,7 @@ static void gen_mov_fp2fp(DisasContext *s, int type, int dst, int src) 
static void disas_fp_csel(DisasContext *s, uint32_t insn)

{

    unsigned int mos, type, rm, cond, rn, rd;

    int label_continue = -1;

    TCGLabel *label_continue = NULL;



    mos = extract32(insn, 29, 3);

    type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
@@ -4184,7 +4184,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn) 
    }



    if (cond < 0x0e) { /* not always */

        int label_match = gen_new_label();

        TCGLabel *label_match = gen_new_label();

        label_continue = gen_new_label();

        arm_gen_test_cc(cond, label_match);

        /* nomatch: */

target-arm/translate.c

+4 −4
Original line number Diff line number Diff line
@@ -736,10 +736,10 @@ static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b) 
 * generate a conditional branch based on ARM condition code cc.

 * This is common between ARM and Aarch64 targets.

 */

void arm_gen_test_cc(int cc, int label)

void arm_gen_test_cc(int cc, TCGLabel *label)

{

    TCGv_i32 tmp;

    int inv;

    TCGLabel *inv;



    switch (cc) {

    case 0: /* eq: Z */
@@ -7440,8 +7440,8 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, 
{

    TCGv_i32 tmp;

    TCGv_i64 val64, extaddr;

    int done_label;

    int fail_label;

    TCGLabel *done_label;

    TCGLabel *fail_label;



    /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {

         [addr] = {Rt};

target-arm/translate.h

+2 −2
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ typedef struct DisasContext { 
    /* Nonzero if this instruction has been conditionally skipped.  */

    int condjmp;

    /* The label that will be jumped to when the instruction is skipped.  */

    int condlabel;

    TCGLabel *condlabel;

    /* Thumb-2 conditional execution bits.  */

    int condexec_mask;

    int condexec_cond;
@@ -119,6 +119,6 @@ static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, 
}

#endif



void arm_gen_test_cc(int cc, int label);

void arm_gen_test_cc(int cc, TCGLabel *label);



#endif /* TARGET_ARM_TRANSLATE_H */