Commit a8a6d53e authored by Nikunj A Dadhania's avatar Nikunj A Dadhania Committed by David Gibson
Browse files

target-ppc: add TLB_NEED_LOCAL_FLUSH flag 



Introduces bit-flag in CPUPPCState::tlb_need_flush:

  TLB_NEED_LOCAL_FLUSH (0x1) - Flush local tlb

This would indicate a pending local tlb flush (isync instructions,
interrupts, ...)

Signed-off-by: default avatarNikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 7ebaf795

target-ppc/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -1009,6 +1009,7 @@ struct CPUPPCState { 
    bool tlb_dirty;   /* Set to non-zero when modifying TLB                  */

    bool kvm_sw_tlb;  /* non-zero if KVM SW TLB API is active                */

    uint32_t tlb_need_flush; /* Delayed flush needed */

#define TLB_NEED_LOCAL_FLUSH   0x1

#endif



    /* Other registers */

target-ppc/helper_regs.h

+2 −2
Original line number Diff line number Diff line
@@ -157,9 +157,9 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, 
static inline void check_tlb_flush(CPUPPCState *env)

{

    CPUState *cs = CPU(ppc_env_get_cpu(env));

    if (env->tlb_need_flush) {

        env->tlb_need_flush = 0;

    if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) {

        tlb_flush(cs, 1);

        env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;

    }

}

#else

target-ppc/mmu-hash64.c

+2 −2
Original line number Diff line number Diff line
@@ -110,7 +110,7 @@ void helper_slbia(CPUPPCState *env) 
             *      and we still don't have a tlb_flush_mask(env, n, mask)

             *      in QEMU, we just invalidate all TLBs

             */

            env->tlb_need_flush = 1;

            env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;

        }

    }

}
@@ -132,7 +132,7 @@ void helper_slbie(CPUPPCState *env, target_ulong addr) 
         *      and we still don't have a tlb_flush_mask(env, n, mask)

         *      in QEMU, we just invalidate all TLBs

         */

        env->tlb_need_flush = 1;

        env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;

    }

}

target-ppc/mmu_helper.c

+3 −3
Original line number Diff line number Diff line
@@ -1965,7 +1965,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) 
         * we just mark the TLB to be flushed later (context synchronizing

         * event or sync instruction on 32-bit).

         */

        env->tlb_need_flush = 1;

        env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;

        break;

#if defined(TARGET_PPC64)

    case POWERPC_MMU_64B:
@@ -1979,7 +1979,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) 
         *      and we still don't have a tlb_flush_mask(env, n, mask) in QEMU,

         *      we just invalidate all TLBs

         */

        env->tlb_need_flush = 1;

        env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;

        break;

#endif /* defined(TARGET_PPC64) */

    default:
@@ -2065,7 +2065,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value) 
            }

        }

#else

        env->tlb_need_flush = 1;

        env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;

#endif

    }

}