Commit a8595957 authored by François Baldassari's avatar François Baldassari Committed by Peter Maydell
Browse files

hw/arm_gic: Correctly restore nested irq priority 




Upon activating an interrupt, set the corresponding priority bit in the
APR/NSAPR registers without touching the currently set bits. In the event
of nested interrupts, the GIC will then have the information it needs to
restore the priority of the pre-empted interrupt once the higher priority
interrupt finishes execution.

Signed-off-by: default avatarFrançois Baldassari <francois@pebble.com>
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 8f280309

hw/intc/arm_gic.c

+2 −2
Original line number Diff line number Diff line
@@ -254,9 +254,9 @@ static void gic_activate_irq(GICState *s, int cpu, int irq) 
    int bitno = preemption_level % 32;



    if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) {

        s->nsapr[regno][cpu] &= (1 << bitno);

        s->nsapr[regno][cpu] |= (1 << bitno);

    } else {

        s->apr[regno][cpu] &= (1 << bitno);

        s->apr[regno][cpu] |= (1 << bitno);

    }



    s->running_priority[cpu] = prio;