Commit a764f3f7 authored by Konrad Rzeszutek Wilk's avatar Konrad Rzeszutek Wilk Committed by Eduardo Habkost
Browse files

i386: define the AMD 'amd-ssbd' CPUID feature bit 

AMD future CPUs expose _two_ ways to utilize the Intel equivalant
of the Speculative Store Bypass Disable. The first is via
the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second
is via the SPEC_CTRL MSR (0x48). The document titled:
124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf

gives priority of SPEC CTRL MSR over the VIRT SPEC CTRL MSR.

A copy of this document is available at
      https://bugzilla.kernel.org/show_bug.cgi?id=199889



Anyhow, this means that on future AMD CPUs there will be  _two_ ways to
deal with SSBD.

Signed-off-by: default avatarKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Message-Id: <20180601153809.15259-2-konrad.wilk@oracle.com>
Signed-off-by: default avatarEduardo Habkost <ehabkost@redhat.com>
parent 9ccb9784

target/i386/cpu.c

+1 −1
Original line number Diff line number Diff line
@@ -1009,7 +1009,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 
            "ibpb", NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, "virt-ssbd", NULL, NULL,

            "amd-ssbd", "virt-ssbd", NULL, NULL,

            NULL, NULL, NULL, NULL,

        },

        .cpuid_eax = 0x80000008,