Commit a61837da authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/shorne/tags/openrisc-20171021-smp-pr' into staging 



OpenRISC SMP patchset 20171021

# gpg: Signature made Fri 20 Oct 2017 22:51:16 BST
# gpg:                using RSA key 0xC3B31C2D5E6627E4
# gpg: Good signature from "Stafford Horne <shorne@gmail.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25  EFF1 C3B3 1C2D 5E66 27E4

* remotes/shorne/tags/openrisc-20171021-smp-pr:
  openrisc: Only kick cpu on timeout, not on update
  openrisc: Initial SMP support
  openrisc/cputimer: Perparation for Multicore
  target/openrisc: Make coreid and numcores variable
  openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC)

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents e822e81e 373b259b

default-configs/or1k-softmmu.mak

+1 −0
Original line number Diff line number Diff line
@@ -2,3 +2,4 @@ 


CONFIG_SERIAL=y

CONFIG_OPENCORES_ETH=y

CONFIG_OMPIC=y

hw/intc/Makefile.objs

+1 −0
Original line number Diff line number Diff line
@@ -43,3 +43,4 @@ obj-$(CONFIG_ASPEED_SOC) += aspeed_vic.o 
obj-$(CONFIG_ARM_GIC) += arm_gicv3_cpuif.o

obj-$(CONFIG_MIPS_CPS) += mips_gic.o

obj-$(CONFIG_NIOS2) += nios2_iic.o

obj-$(CONFIG_OMPIC) += ompic.o

hw/intc/ompic.c

0 → 100644
+179 −0
Original line number Diff line number Diff line 
/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Authors: Stafford Horne <shorne@gmail.com>

 */



#include "qemu/osdep.h"

#include "qemu/log.h"

#include "qapi/error.h"

#include "hw/hw.h"

#include "hw/sysbus.h"

#include "exec/memory.h"



#define TYPE_OR1K_OMPIC "or1k-ompic"

#define OR1K_OMPIC(obj) OBJECT_CHECK(OR1KOMPICState, (obj), TYPE_OR1K_OMPIC)



#define OMPIC_CTRL_IRQ_ACK  (1 << 31)

#define OMPIC_CTRL_IRQ_GEN  (1 << 30)

#define OMPIC_CTRL_DST(cpu) (((cpu) >> 16) & 0x3fff)



#define OMPIC_REG(addr)     (((addr) >> 2) & 0x1)

#define OMPIC_SRC_CPU(addr) (((addr) >> 3) & 0x4f)

#define OMPIC_DST_CPU(addr) (((addr) >> 3) & 0x4f)



#define OMPIC_STATUS_IRQ_PENDING (1 << 30)

#define OMPIC_STATUS_SRC(cpu)    (((cpu) & 0x3fff) << 16)

#define OMPIC_STATUS_DATA(data)  ((data) & 0xffff)



#define OMPIC_CONTROL 0

#define OMPIC_STATUS  1



#define OMPIC_MAX_CPUS 4 /* Real max is much higher, but dont waste memory */

#define OMPIC_ADDRSPACE_SZ (OMPIC_MAX_CPUS * 2 * 4) /* 2 32-bit regs per cpu */



typedef struct OR1KOMPICState OR1KOMPICState;

typedef struct OR1KOMPICCPUState OR1KOMPICCPUState;



struct OR1KOMPICCPUState {

    qemu_irq irq;

    uint32_t status;

    uint32_t control;

};



struct OR1KOMPICState {

    SysBusDevice parent_obj;

    MemoryRegion mr;



    OR1KOMPICCPUState cpus[OMPIC_MAX_CPUS];



    uint32_t num_cpus;

};



static uint64_t ompic_read(void *opaque, hwaddr addr, unsigned size)

{

    OR1KOMPICState *s = opaque;

    int src_cpu = OMPIC_SRC_CPU(addr);



    /* We can only write to control control, write control + update status */

    if (OMPIC_REG(addr) == OMPIC_CONTROL) {

        return s->cpus[src_cpu].control;

    } else {

        return s->cpus[src_cpu].status;

   }



}



static void ompic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)

{

    OR1KOMPICState *s = opaque;

    /* We can only write to control control, write control + update status */

    if (OMPIC_REG(addr) == OMPIC_CONTROL) {

        int src_cpu = OMPIC_SRC_CPU(addr);



        s->cpus[src_cpu].control = data;



        if (data & OMPIC_CTRL_IRQ_GEN) {

            int dst_cpu = OMPIC_CTRL_DST(data);



            s->cpus[dst_cpu].status = OMPIC_STATUS_IRQ_PENDING |

                OMPIC_STATUS_SRC(src_cpu) |

                OMPIC_STATUS_DATA(data);



            qemu_irq_raise(s->cpus[dst_cpu].irq);

        }

        if (data & OMPIC_CTRL_IRQ_ACK) {

            s->cpus[src_cpu].status &= ~OMPIC_STATUS_IRQ_PENDING;

            qemu_irq_lower(s->cpus[src_cpu].irq);

        }

    }

}



static const MemoryRegionOps ompic_ops = {

    .read = ompic_read,

    .write = ompic_write,

    .endianness = DEVICE_NATIVE_ENDIAN,

    .impl = {

        .max_access_size = 8,

    },

};



static void or1k_ompic_init(Object *obj)

{

    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

    OR1KOMPICState *s = OR1K_OMPIC(obj);



    memory_region_init_io(&s->mr, OBJECT(s), &ompic_ops, s,

                          "or1k-ompic", OMPIC_ADDRSPACE_SZ);

    sysbus_init_mmio(sbd, &s->mr);

}



static void or1k_ompic_realize(DeviceState *dev, Error **errp)

{

    OR1KOMPICState *s = OR1K_OMPIC(dev);

    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);

    int i;



    if (s->num_cpus > OMPIC_MAX_CPUS) {

        error_setg(errp, "Exceeded maximum CPUs %d", s->num_cpus);

        return;

    }

    /* Init IRQ sources for all CPUs */

    for (i = 0; i < s->num_cpus; i++) {

        sysbus_init_irq(sbd, &s->cpus[i].irq);

    }

}



static Property or1k_ompic_properties[] = {

    DEFINE_PROP_UINT32("num-cpus", OR1KOMPICState, num_cpus, 1),

    DEFINE_PROP_END_OF_LIST(),

};



static const VMStateDescription vmstate_or1k_ompic_cpu = {

    .name = "or1k_ompic_cpu",

    .version_id = 1,

    .minimum_version_id = 1,

    .fields = (VMStateField[]) {

         VMSTATE_UINT32(status, OR1KOMPICCPUState),

         VMSTATE_UINT32(control, OR1KOMPICCPUState),

         VMSTATE_END_OF_LIST()

    }

};



static const VMStateDescription vmstate_or1k_ompic = {

    .name = TYPE_OR1K_OMPIC,

    .version_id = 1,

    .minimum_version_id = 1,

    .fields = (VMStateField[]) {

         VMSTATE_STRUCT_ARRAY(cpus, OR1KOMPICState, OMPIC_MAX_CPUS, 1,

             vmstate_or1k_ompic_cpu, OR1KOMPICCPUState),

         VMSTATE_UINT32(num_cpus, OR1KOMPICState),

         VMSTATE_END_OF_LIST()

    }

};



static void or1k_ompic_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);



    dc->props = or1k_ompic_properties;

    dc->realize = or1k_ompic_realize;

    dc->vmsd = &vmstate_or1k_ompic;

}



static const TypeInfo or1k_ompic_info = {

    .name          = TYPE_OR1K_OMPIC,

    .parent        = TYPE_SYS_BUS_DEVICE,

    .instance_size = sizeof(OR1KOMPICState),

    .instance_init = or1k_ompic_init,

    .class_init    = or1k_ompic_class_init,

};



static void or1k_ompic_register_types(void)

{

    type_register_static(&or1k_ompic_info);

}



type_init(or1k_ompic_register_types)

hw/openrisc/cputimer.c

+48 −16
Original line number Diff line number Diff line
@@ -25,48 +25,64 @@ 


#define TIMER_PERIOD 50 /* 50 ns period for 20 MHz timer */



/* The time when TTCR changes */

static uint64_t last_clk;

static int is_counting;

/* Tick Timer global state to allow all cores to be in sync */

typedef struct OR1KTimerState {

    uint32_t ttcr;

    uint64_t last_clk;

} OR1KTimerState;



static OR1KTimerState *or1k_timer;



void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val)

{

    or1k_timer->ttcr = val;

}



uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu)

{

    return or1k_timer->ttcr;

}



/* Add elapsed ticks to ttcr */

void cpu_openrisc_count_update(OpenRISCCPU *cpu)

{

    uint64_t now;



    if (!is_counting) {

    if (!cpu->env.is_counting) {

        return;

    }

    now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);

    cpu->env.ttcr += (uint32_t)((now - last_clk) / TIMER_PERIOD);

    last_clk = now;

    or1k_timer->ttcr += (uint32_t)((now - or1k_timer->last_clk)

                                    / TIMER_PERIOD);

    or1k_timer->last_clk = now;

}



/* Update the next timeout time as difference between ttmr and ttcr */

void cpu_openrisc_timer_update(OpenRISCCPU *cpu)

{

    uint32_t wait;

    uint64_t now, next;



    if (!is_counting) {

    if (!cpu->env.is_counting) {

        return;

    }



    cpu_openrisc_count_update(cpu);

    now = last_clk;

    now = or1k_timer->last_clk;



    if ((cpu->env.ttmr & TTMR_TP) <= (cpu->env.ttcr & TTMR_TP)) {

        wait = TTMR_TP - (cpu->env.ttcr & TTMR_TP) + 1;

    if ((cpu->env.ttmr & TTMR_TP) <= (or1k_timer->ttcr & TTMR_TP)) {

        wait = TTMR_TP - (or1k_timer->ttcr & TTMR_TP) + 1;

        wait += cpu->env.ttmr & TTMR_TP;

    } else {

        wait = (cpu->env.ttmr & TTMR_TP) - (cpu->env.ttcr & TTMR_TP);

        wait = (cpu->env.ttmr & TTMR_TP) - (or1k_timer->ttcr & TTMR_TP);

    }

    next = now + (uint64_t)wait * TIMER_PERIOD;

    timer_mod(cpu->env.timer, next);

    qemu_cpu_kick(CPU(cpu));

}



void cpu_openrisc_count_start(OpenRISCCPU *cpu)

{

    is_counting = 1;

    cpu->env.is_counting = 1;

    cpu_openrisc_count_update(cpu);

}
@@ -74,7 +90,7 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu) 
{

    timer_del(cpu->env.timer);

    cpu_openrisc_count_update(cpu);

    is_counting = 0;

    cpu->env.is_counting = 0;

}



static void openrisc_timer_cb(void *opaque)
@@ -93,7 +109,7 @@ static void openrisc_timer_cb(void *opaque) 
    case TIMER_NONE:

        break;

    case TIMER_INTR:

        cpu->env.ttcr = 0;

        or1k_timer->ttcr = 0;

        break;

    case TIMER_SHOT:

        cpu_openrisc_count_stop(cpu);
@@ -103,11 +119,27 @@ static void openrisc_timer_cb(void *opaque) 
    }



    cpu_openrisc_timer_update(cpu);

    qemu_cpu_kick(CPU(cpu));

}



static const VMStateDescription vmstate_or1k_timer = {

    .name = "or1k_timer",

    .version_id = 1,

    .minimum_version_id = 1,

    .fields = (VMStateField[]) {

        VMSTATE_UINT32(ttcr, OR1KTimerState),

        VMSTATE_UINT64(last_clk, OR1KTimerState),

        VMSTATE_END_OF_LIST()

    }

};



void cpu_openrisc_clock_init(OpenRISCCPU *cpu)

{

    cpu->env.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &openrisc_timer_cb, cpu);

    cpu->env.ttmr = 0x00000000;

    cpu->env.ttcr = 0x00000000;



    if (or1k_timer == NULL) {

        or1k_timer = g_new0(OR1KTimerState, 1);

        vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer);

    }

}

hw/openrisc/openrisc_sim.c

+65 −23
Original line number Diff line number Diff line
@@ -35,36 +35,60 @@ 


#define KERNEL_LOAD_ADDR 0x100



static struct openrisc_boot_info {

    uint32_t bootstrap_pc;

} boot_info;



static void main_cpu_reset(void *opaque)

{

    OpenRISCCPU *cpu = opaque;

    CPUState *cs = CPU(cpu);



    cpu_reset(CPU(cpu));



    cpu_set_pc(cs, boot_info.bootstrap_pc);

}



static void openrisc_sim_net_init(MemoryRegion *address_space,

                                  hwaddr base,

                                  hwaddr descriptors,

                                  qemu_irq irq, NICInfo *nd)

static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors,

                                  int num_cpus, qemu_irq **cpu_irqs,

                                  int irq_pin, NICInfo *nd)

{

    DeviceState *dev;

    SysBusDevice *s;

    int i;



    dev = qdev_create(NULL, "open_eth");

    qdev_set_nic_properties(dev, nd);

    qdev_init_nofail(dev);



    s = SYS_BUS_DEVICE(dev);

    sysbus_connect_irq(s, 0, irq);

    memory_region_add_subregion(address_space, base,

                                sysbus_mmio_get_region(s, 0));

    memory_region_add_subregion(address_space, descriptors,

                                sysbus_mmio_get_region(s, 1));

    for (i = 0; i < num_cpus; i++) {

        sysbus_connect_irq(s, 0, cpu_irqs[i][irq_pin]);

    }

    sysbus_mmio_map(s, 0, base);

    sysbus_mmio_map(s, 1, descriptors);

}



static void cpu_openrisc_load_kernel(ram_addr_t ram_size,

                                     const char *kernel_filename,

                                     OpenRISCCPU *cpu)

static void openrisc_sim_ompic_init(hwaddr base, int num_cpus,

                                    qemu_irq **cpu_irqs, int irq_pin)

{

    DeviceState *dev;

    SysBusDevice *s;

    int i;



    dev = qdev_create(NULL, "or1k-ompic");

    qdev_prop_set_uint32(dev, "num-cpus", num_cpus);

    qdev_init_nofail(dev);



    s = SYS_BUS_DEVICE(dev);

    for (i = 0; i < num_cpus; i++) {

        sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]);

    }

    sysbus_mmio_map(s, 0, base);

}



static void openrisc_load_kernel(ram_addr_t ram_size,

                                 const char *kernel_filename)

{

    long kernel_size;

    uint64_t elf_entry;
@@ -83,6 +107,9 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size, 
            kernel_size = load_image_targphys(kernel_filename,

                                              KERNEL_LOAD_ADDR,

                                              ram_size - KERNEL_LOAD_ADDR);

        }



        if (entry <= 0) {

            entry = KERNEL_LOAD_ADDR;

        }
@@ -91,7 +118,7 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size, 
                    kernel_filename);

            exit(1);

        }

        cpu->env.pc = entry;

        boot_info.bootstrap_pc = entry;

    }

}
@@ -102,6 +129,8 @@ static void openrisc_sim_init(MachineState *machine) 
    const char *kernel_filename = machine->kernel_filename;

    OpenRISCCPU *cpu = NULL;

    MemoryRegion *ram;

    qemu_irq *cpu_irqs[2];

    qemu_irq serial_irq;

    int n;



    if (!cpu_model) {
@@ -110,33 +139,46 @@ static void openrisc_sim_init(MachineState *machine) 


    for (n = 0; n < smp_cpus; n++) {

        cpu = OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model));

        if (cpu == NULL) {

            fprintf(stderr, "Unable to find CPU definition!\n");

            exit(1);

        }

        cpu_openrisc_pic_init(cpu);

        cpu_irqs[n] = (qemu_irq *) cpu->env.irq;



        cpu_openrisc_clock_init(cpu);



        qemu_register_reset(main_cpu_reset, cpu);

        main_cpu_reset(cpu);

    }



    ram = g_malloc(sizeof(*ram));

    memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal);

    memory_region_add_subregion(get_system_memory(), 0, ram);



    cpu_openrisc_pic_init(cpu);

    cpu_openrisc_clock_init(cpu);

    if (nd_table[0].used) {

        openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus,

                              cpu_irqs, 4, nd_table);

    }



    serial_mm_init(get_system_memory(), 0x90000000, 0, cpu->env.irq[2],

                   115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);

    if (smp_cpus > 1) {

        openrisc_sim_ompic_init(0x98000000, smp_cpus, cpu_irqs, 1);



    if (nd_table[0].used) {

        openrisc_sim_net_init(get_system_memory(), 0x92000000,

                              0x92000400, cpu->env.irq[4], nd_table);

        serial_irq = qemu_irq_split(cpu_irqs[0][2], cpu_irqs[1][2]);

    } else {

        serial_irq = cpu_irqs[0][2];

    }



    cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);

    serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq,

                   115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);



    openrisc_load_kernel(ram_size, kernel_filename);

}



static void openrisc_sim_machine_init(MachineClass *mc)

{

    mc->desc = "or1k simulation";

    mc->init = openrisc_sim_init;

    mc->max_cpus = 1;

    mc->max_cpus = 2;

    mc->is_default = 1;

}